7.3.4 Digital Output

A differential input signal of 0 V ideally produces a stream of ones and zeros that are high 50% of the time.

A differential input of 250 mV produces a stream of ones and zeros that are high 89.06% of the time. With 16

bits of resolution, that percentage ideally corresponds to code 58368. A differential input of –250 mV produces a

stream of ones and zeros that are high 10.94% of the time and ideally results in code 7168 with 16-bit resolution.

These input voltages are also the specified linear range of the AMC1306M25-Q1. If the input voltage value

exceeds this range, the output of the modulator shows nonlinear behavior as the quantization noise increases.

The output of the modulator clips with a constant stream of zeros with an input less than or equal to –320

mV or with a constant stream of ones with an input greater than or equal to 320 mV. In this case, however,

the AMC1306M25-Q1 generates a single 1 (if the input is at negative full-scale) or 0 (if the input is at positive

full-scale) every 128 clock cycles to indicate proper device function (see the Output Behavior in Case of a

Full-Scale Input section for more details). Figure 7-4 shows the input voltage versus the output modulator signal.

Modulator Output

+ FS (Analog Input)

– FS (Analog Input)

Analog Input

Figure 7-4. AMC1306M25-Q1 Modulator Output vs Analog Input

2×VClipping

(1)

7.3.4.1 Output Behavior in Case of a Full-Scale Input

single one or zero every 128 bits at DOUT, as shown in Figure 7-5, depending on the actual polarity of the signal

being sensed. In this way, differentiating between a missing AVDD and a full-scale input signal is possible on the

system level.

DOUT

CLKIN

127 CLKIN cycles

127 CLKIN cycles

–320 mV

DOUT

Figure 7-5. Output of the AMC1306M25-Q1 in Case of an Input Overrange

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