NXP Semiconductors

FS8600_SDS

Fail-safe system basis chip with multiple SMPSs and LDOs

7 Pinout information

7.1 Pinout

NC

1

48 47 46 45 44 43 42

EXPOSED PAD

FS86 in QFN 48

40 39 38 37

41

13 14 15 16 17 18 19

21 22 23 24

20

36

35

34

33

32

31

30

29

28

27

26

25

ERRMON

PRE_GLS

PRE_SW

PRE_GHS

PRE_BOOT

VMON5_RES

PRE_COMP

INTB

SDA

OTP

SCL

VMON0_I2C

FOUT

Power management

aaa-043503

Communication

Safety

Other

LDO1_IN

2

LDO1

3

FCCU2

4

FCCU1

5

BOOST_LS

6

BUCK_SW

7

BUCK_IN

8

BAT_SW

9

VMON6_RES 10

BUCK_FB

VMON7_RES 12

11

Figure 3. Pin configuration

7.2 Pin description

Pin

Name

Type

Description

1

N/C

N/C

Not connected pin

2

LDO1_IN

Analog input

Linear regulator #1 input voltage

3

LDO1

Analog output

Linear regulator #1 output voltage

4

FCCU2

Digital input

MCU Error Monitoring input 2

5

FCCU1

Digital input

MCU Error Monitoring input 1

6

BOOST_LS

Analog input

BOOST Low Side Drain of internal MOSFET

7

BUCK_SW

Analog output

Low Voltage Buck switching node

8

BUCK_IN

Analog input

Low Voltage Buck input voltage

9

BAT_SW

Digital output

Battery switch control output. Active Low. Open drain structure.

10

VMON6_RES

Analog input

External resistor bridge voltage monitoring input #6

Table 3. Pin description

FS8600_SDS

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© NXP B.V. 2021. All rights reserved.

Product short data sheet

Rev. 1.1 — 23 November 2021

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