SP9841 datasheet(25/32 Pages) SIPEX

25 / 32 page

291

rail–to–rail output swing. In order to obtain this

performance, V

REFL must be externally driven to

DD/2, perhaps by use of the circuit of Figure 11.

At V

REFL near 2.5V and VDD = 4.75V, the typical

positive output headroom at the DAC is limited

to 1.15V above 2.5V, so that this circuit is useful

for rail–to–rail outputs for gains higher than

4.35 (i.e. 1.15V

PP maximum input). Note that

while an AC–coupled input is shown, this cir-

cuit is just as useful for DC–coupled inputs

which are generated with respect to the V

REFL

pseudoground voltage. R

IBIAS is used for the

AC–coupled circuit for opamp bias current re-

turn when the DAC is programmed to code 0, as

no current flows into V

IN(X) at code 0.

Figure 11 shows a minimal parts count method

Figure 11. Programmable, Bootstrapped, 1.4V to 2.2V V

REFL Drive.

The usable range for the bootstrapped V

REFL circuit is 1.4 to 2.4VOUT at VDD = 5V, RISRC = 2kOhms.

To increase the upper usable limit, decrease value of R

ISRC.

–

OUTA

1/8 of SP9841

ICL8069

At PRESET, V

OUT = 1.3V

(not well–regulated)

RISRC

2kOhm

Load code

45µF*

301Ohm

1.22V

–

REFL

INA

–

1/8 of SP9841

INB

*(Optional Noise Reduction)

+5V

112 for 1.4V

OUT = VREFL

96 for 1.6V

OUT = VREFL

70 for 2.2V

OUT = VREFL

OUTB

–

1/8 of SP9841

INH

OUTH

SP9841 bảng dữ liệu(PDF) 25 Page - Sipex Corporation

SP9841 bảng dữ liệu(HTML) 25 Page - Sipex Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

bảng dữ liệu tải về

Link URL