264

the specified load resistance and capacitance. The

reference inputs are useful for both AC and DC input

sources. However, series resistance into these pins

will degrade the linearity of the DAC — 50 Ohms of

series resistance can cause up to 0.5LSB of additional

integral linearity degradation for codes near zero, due

to the code–dependent input current dropping across

thiserrorresistance.AC–coupledapplicationsshould

use the largest capacitor value (lowest series imped-

ance) which is practical, or use an external buffer to

drive the inputs.

The DAC switches function in a break–before–make

manner in order to minimize current spikes at the

reference inputs. The reference inputs can withstand

driving voltages slightly beyond the power rails with-

out harm; the gain of

±1 at the op amps limits the

choice of V

avoidedatveryhighorverylowcodes.Notethatrail–

to–rail inputs can always be attenuated by choosing a

code nearer midscale, if clipping of the output is

undesirable.

Output Considerations

Each DAC output amplifier can easily drive 1Kohm

loads in parallel with 15pF at its rated slew rate. The

uniqueBiCMOSamplifierdesignalsoensuresstabil-

ity into heavily capacitive loads — up to 47,000pF.

Undertheseconditions,theslewratewillbelimitedby

the instantaneous current available for charging the

capacitance—theslewratewillbeseverelydegraded,

and some damped ringing will occur. Especially

under heavy capacitive loading, a large, low imped-

ancelocalbypasscapacitorwillberequired.A0.047

µF

ceramic in parallel with a low–ESR 2.2 to 10

µF

tantalum are recommended for worst–case loads.

The amplifier outputs can withstand momentary

shorts to V

operation can result in thermally induced damage,

and should be avoided.

If the input reference voltage is reduced to 0.6V, then

both the amplifier and DAC are functional at room

temperatureatsupplyvoltagesaslowas2.5V.AtV

DD

= 2.7V, power dissipation is 9.3mW typical, with the

serialclockat4MHz,or7.0mWtypicalwiththeserial

clock gated off.

Interfacing to the SP9840/SP9843

A simple serial interface, similar to that used in a

74HC594 shift–register with output latch, has been

implemented in these products. A serial clock is used

to strobe serial data into a 12–stage shift–register at

eachrisingclockedge.Thefirstfourserialbitscontain

the address of the DAC to be updated, MSB first. The

next 8 bits contain the binary value to be loaded into

thedesiredDAC,againMSBfirst.Afterthe12thserial

bit is clocked in, the LOADH line can be strobed to

latch the 8 bits of data into the data holding register for

the desired DAC. The address bits feed a decoding

network which steers the LOADH pulse to the clock

input of the desired DAC data holding register. The

output of the 12th shift–register is also buffered and

brought out as the SERIAL DATA OUT (SDO),

which can be used to cascade multiple devices, or for

data verification purposes.

The address field is set up such that DACA is ad-

dressed at 0001 (binary) and the others consecutively

through DACH at 1000(binary). Address 0000(bi-

nary) will not affect the operation of any channel, as

this combination is easily generated inadvertently at

power–up. Other no–operation addresses exist at

1001(binary) through 1111(binary). Another use for

no–operation addresses is to mask off updates of any

DAC channel in a multiple–part system with cas-

caded serial inputs and outputs. By sending a valid

address and data only to the desired channel, it is

possible to simplify the system hardware by driving

the LOADH pin at each part in parallel from a single

source. Table 1 shows a register–level diagram of the

addresses, data, and the resulting operation.

A fourth control pin, PRESETL, can be used to

simultaneously preset all DAC data holding registers

to their mid–scale (80

nously force all DAC outputs to buffer the voltages at

their respective inputs to their outputs with unity gain.

This feature is useful at power–up, asa simple resistor

to the supply and capacitor to ground can insure that

all DAC outputs start at a known voltage. For four–

channel multiplying applications, this sets the default

start–upgaintozero;only–70dBoffeedthroughfrom

the V

2 summarizes the operation of the four digital inputs.