SIC437 datasheet(21/27 Pages) VISHAY

21 / 27 page

SiC437, SiC438

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Vishay Siliconix

S20-0679-Rev. D, 27-Aug-2020

Document Number: 75921

For technical questions, contact: powerictechsupport@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

PCB LAYOUT RECOMMENDATIONS

Step 1: VIN/GND Planes and Decoupling

1. Layout VIN and PGND planes as shown above

2. Ceramic capacitors should be placed between VIN and

PGND, and very close to the device for best decoupling

effect

3. Various ceramic capacitor values and package sizes

should be used to cover entire decoupling spectrum e.g.

1210 and 0603

4. Smaller capacitance values, closer to VIN pin(s), provide

better high frequency response

Step 2: SW Plane

1. Connect output inductor to device with large plane to

lower resistance

2. If a snubber network is required, place the components

on the bottom layer as shown above

Step 3: VDD/VDRV Input Filter

1. CVDD cap should be placed between VDD and AGND to

achieve best noise filtering

2. CVDRV cap should be placed close to VDRV and PGND pins

to reduce effects of trace impedance and provide

maximum instantaneous driver current for low side

MOSFET during switching cycle

Step 4: BOOT Resistor and Capacitor Placement

1. CBOOT and RBOOT need to be placed very close to the

device, between PHASE and BOOT pins

2. In

order

reduce

parasitic

inductance,

recommended to use 0402 chip size for the resistor and

the capacitor

VIN plane

PGND plane

AGND

VDD

VDRV

PGND

Cboot

Rboot

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