Data Sheet

ADP2503/ADP2504

Rev. D | Page 15 of 16

PCB LAYOUT GUIDELINES

Poor layout can affect ADP2503/ADP2504 performance, causing

electromagnetic interference (EMI) and electromagnetic

compatibility (EMC) performance, ground bounce, and voltage

losses. Poor layout can also affect regulation and stability. A good

layout is implemented using the following rules:



Place the inductor, input capacitor, and output capacitor

close to the IC using short tracks. These components carry

high switching frequencies and large tracks act like antennas.



Route the output voltage path away from the inductor and

SW node to minimize noise and magnetic interference.



Maximize the size of ground metal on the component side

to help with thermal dissipation.



Use a ground plane with several vias connecting to the

component side ground to further reduce noise interference

on sensitive circuit nodes.

Figure 31. ADP2503/ADP2504 Evaluation Board for Fixed Output Voltages