ADP1031ACPZ-5-R7 datasheet(27/38 Pages) AD

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Data Sheet

ADP1031

Rev. A | Page 27 of 38

THERMAL SHUTDOWN

If the ADP1031 junction temperature rises above TSHDN, the

thermal shutdown circuit turns the flyback regulator off.

Extreme junction temperatures can be the result of prolonged

high current operation, poor circuit board design, and/or high

ambient temperatures. When thermal shutdown occurs, hysteresis

is included so that the ADP1031 does not return to operation until

the on-chip temperature drops below TSHDN − THYS. When resuming

from thermal shutdown, the ADP1031 performs a soft start.

DATA ISOLATION

High Speed SPI Channels

The ADP1031 has four high speed channels. The first three, CLK,

MI/SO, and MO/SI (the slash indicates the connection of the input

and output forming a datapath across the isolator that corresponds to

an SPI bus signal) are optimized for low propagation delay.

With a maximum propagation delay of 15 ns, the ADP1031

supports read and write clock rates up to 16.6 MHz in the standard

4-wire SPI. However, the total round trip delay of the system

determines the maximum clock rate and is less than that value.

The relationship between the SPI signal paths, the ADP1031 pin

mnemonics, and the data directions are detailed in Table 12.

Table 12. Correspondence of the Pin Mnemonics to the SPI

Signal Path Names

SPI Signal Path

Master Side

Data Direction

Slave Side

CLK

MCK

→

SCK

MO/SI

→

MI/SO

←

MSS

→

SSS

The datapaths are SPI mode agnostic. The CLK and MO/SI SPI

datapaths are optimized for propagation delay and channel to

channel matching. The MI/SO SPI datapath is optimized for

propagation delay. The device does not synchronize to the clock

channels. Therefore, there are no constraints on the clock

polarity or timing with respect to the data lines.

SS (slave select bar) is an active low signal. To save power in a

multichannel system, SS puts the other SPI isolator channels in

a low power state when the channels are not in use (SS = high),

and these channels are only active when required, which is

when SS is low. The clock and data channels are gated to the SS

as shown in Figure 67. However, this power saving mode adds

100 ns of latency. This latency is the time required for the internal

circuitry to wake up from the low power state and to start

transmitting data to the isolation barrier. Conversely, the

latency is the delay from the falling edge of MSS to the first

clock edge or data edge that appears on the slave side, as shown

in Figure 68.

DECODE

ENCODE

DECODE

ENCODE

DECODE

ENCODE

DECODE

MSS

MCK

SSS

SCK

Figure 67. iCoupler Gating

SSS

SCK, SI, MI

MCK, MO, SO

HIGH IMPEDANCE

ADD A PULL HIGH OR PULL LOW RESISTOR

TO HAVE A KNOWN STATE WHEN MSS IS HIGH.

LATENCY = MSS FALLING EDGE TO SCK, SI, MI STARTS SENDING DATA (EXIT TO HIGH IMPEDANCE MODE).

tPW = MCK, MO, SO PULSE WIDTH.

tP1 = MSS TO SSS PROPAGATION DELAY.

tP2 = MCK TO SCK, MO TO SI, SO TO MI PROPAGATION DELAY.

tP3 = MSS RISING EDGE TO SCK, SI, MI RETURN TO HIGH IMPEDANCE STATE. SAME AS tP1.

MSS

tP1

tP2

tPW

SPI

ACTIVATION

(LATENCY)

SPI TRANSMIT

tP3

Figure 68. SPI Isolators Timing Diagram

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