ADMV8913-EP

Enhanced Product

Rev. 0 | Page 22 of 23

Register: 0x020, Reset: 0x00, Name: WR

SPI Write: HPF State

SPI Write: LPF State

0

0

1

0

2

0

3

0

4

0

5

0

6

0

7

0

[7:4] HPF_WR (R/W)

[3:0] LPF_WR (R/W)

Table 16. Bit Descriptions for WR

Bits

Bit Name

Description

Reset

Access

[7:4]

HPF_WR

SPI Write: HPF State

0x0

R/W

[3:0]

LPF_WR

SPI Write: LPF State

0x0

R/W

Register: 0x100, Reset: 0x00, Name: LUT0

Note that the LUT1 to LUT127 bit field functionality (Register 0x101 to Register 0x17F) is identical to LUT0 bit field functionality

(Register 0x100). See the Register Summary section and Table 6 for the register address information.

LUT 000: HPF State

LUT 000: LPF State

0

0

1

0

2

0

3

0

4

0

5

0

6

0

7

0

[7:4] HPF_0 (R/W)

[3:0] LPF_0 (R/W)

Table 17. Bit Descriptions for LUT0

Bits

Bit Name

Description

Reset

Access

[7:4]

HPF_0

LUT 000: HPF State

0x0

R/W

[3:0]

LPF_0

LUT 000: LPF State

0x0

R/W