AD3552R datasheet(34/68 Pages) AD

34 / 68 page

Data Sheet

AD3552R

THEORY OF OPERATION

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Rev. A | 34 of 68

Quad SPI Mode

In quad SPI mode, the SDI/SDIO0, SDO/SDIO1, SDIO2, and

SDIO3 data lines are bidirectional, as shown in Figure 84. During

the data phase, the R/W bit of the instruction phase defines the di-

rection of the data lines. During the instruction phase, the data lines

are always configured as inputs. In quad SPI mode, consecutive

bits are serialized in groups of four, as shown in Figure 85.

Figure 84. Quad SPI Connection

Figure 85. Quad SPI Mode

Double Data Rate (DDR)

Irrespective of the SPI mode being used, DDR can be enabled by

setting the SPI_CONFIG_DDR bit in the INTERFACE_CONFIG_D

clock edges, as shown in Figure 86. After this mode is enabled, all

data must be written using DDR.

DDR is only usable in the data phase during write operations. In

readback operations, the SPI_CONFIG_DDR bit is ignored, and

data is transferred from the AD3552R to the controller in single data

rate, as shown in Figure 2, Figure 6, and Figure 10.

After changing the SPI mode or the SPI_CONFIG_DDR bit, CS

must be brought high and a new access cycle must be started in

the appropriate mode.

All valid SPI mode combinations are listed in Table 12.

Figure 86. Quad SPI Mode DDR on a 24-Bit Register

Table 12. SPI Mode Combinations

SPI Mode

MULTI_IO_MODE

DUAL_SPI_SYNCHRONOUS_EN

SPI_CONFIG_DDR

Single SPI SDR

Single SPI DDR

Dual SPI SDR

Dual SPI DDR

Synchronous Dual SPI SDR

Synchronous Dual SPI DDR

Quad SPI SDR1

Not applicable

Quad SPI DDR1

Not applicable

1 Enabled by the QSPI pin only.

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