ADA4254ACPZ-R7 datasheet(48/59 Pages) AD

48 / 59 page

ADA4254

Data Sheet

Rev. B | Page 48 of 59

INTERNAL MUX CONTROL REGISTER (INPUT_MUX) DETAILS

Table 19. INPUT_MUX Register Details (Register 0x06)

Bit Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

SW_A1

SW_A2

SW_B1

SW_B2

SW_C1

SW_C2

SW_D12

Access

Reserved

Reset

Reserved

+IN1

–IN1

+IN2

–IN2

D12

–OUT

PGIA

+OUT

TEST MULTIPLEXER

TEST_MUX[3:0]

AVSS

DVSS

+20mV –20mV

Figure 106. Input Mux Switch Configuration

Bit 6, SW_A1, and Bit 5, SW_A2—Channel 1 Input

Switches

The SW_A1 bit and the SW_A2 bit control the Channel 1 input

switches, A1 and A2, respectively (see Figure 106). Setting these

bits to 1 closes the respective switch. SW_A1 and SW_A2

cannot be connected at the same time as SW_B1 and SW_B2,

unless the MUX_PROT_DIS bit is set to 1.

Bit 4, SW_B1, and Bit 3, SW_B2—Channel 2 Input

Switches

The SW_B1 bit and the SW_B2 bit control the Channel 2 input

switches, B1 and B2, respectively (see Figure 106). Setting these

bits to 1 closes the respective switch. SW_B1 and SW_B2

cannot be connected at the same time as SW_A1 and SW_A2,

unless the MUX_PROT_DIS bit is set to 1.

Bit 2, SW_C1, and Bit 1, SW_C2—PGIA Input Test

Multiplexer Switches

The SW_C1 bit and the SW_C2 bit can be set to 1 to connect

either PGIA input to the output of the input test multiplexer

(which is AVSS by default) via the C1 and C2 switches (see

Figure 106).

Bit 0, SW_D12—PGIA Input Short Switch

The SW_D12 bit can be set to 1 to connect both PGIA inputs

together via the D12 switch.

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