INA159 datasheet(16/28 Pages) TI

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9.1.4 Differential Input Voltage Limitations

Although the INA851 is well protected against overvoltage transients on the inputs, make sure to take proper

design precautions if the device is implemented in an application where high differential voltages are expected.

These precautions apply even if the VIN+ and VIN– voltages do not exceed the device supply rails, and are

especially important if input stage gain GIN is greater than 3 V/V. As the gain increases, the size of gain resistor

RG decreases, and the same differential voltage across the inputs results in more current forced through the

input architecture. Therefore, limit the differential voltage according to Equation 3.

VDIFFmax= VIN+–VIN– =

VS+80V,GIN=1

VS,1<GIN≤3

VSGIN,3<GIN≤40andVSGIN>1V

1V,GIN>40orVSGIN≤1V

(3)

For example, if the supply voltage is ±18 V and the gain is 9 V/V, keep the magnitude of the input differential

voltage less than 4 V. If the supply voltage is ±8 V and the gain is 5 V/V, keep the input differential voltage less

than 3.2 V to make sure that the inputs are protected.

If differential input voltages greater than these limitations are expected, include external input resistors series

with each input to limit the input current to 10 mA or less. The value of these resistors may be calculated using

Equation 4.

RIN≥12 VDIFF–0.6V

10mA –RG

(4)

Low-leakage antiparallel diodes across the IN+ and IN– pins may also be an option in some cases.

INA851

SBOS999 – MARCH 2022

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