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AD5413 bảng dữ liệu(PDF) 7 Page - Analog Devices

tên linh kiện AD5413
Giải thích chi tiết về linh kiện  Single-Channel, 14-Bit Voltage and Current Output DAC with HART Connectivity
PDF  49 Pages
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nhà sản xuất  AD [Analog Devices]
Trang chủ  http://www.analog.com
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AD5413 bảng dữ liệu(HTML) 7 Page - Analog Devices

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Data Sheet
AD5413
Rev. 0 | Page 7 of 49
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
AIDD26
3.3
mA
Voltage output mode
2.9
mA
Current output mode
AISS6
−1.1
mA
Voltage output mode
−0.23
mA
Current output mode (unipolar)
Current Drawn from VLOGIC Supply
(ILOGIC)
0.01
mA
VIH is the voltage on the VLOGIC pin, VIL = DGND
Power Dissipation
Power dissipation assuming an ideal power
supply and excluding the external load
power dissipation
108
mW
AVDD1 = 24 V, AVDD2 = 5 V, AVSS = −15 V,
RLOAD = 1 kΩ, IOUT = 20 mA
505
mW
AVDD1 = 24 V, AVDD2 = 5 V, AVSS = −15 V,
RLOAD = 0 Ω, IOUT = 20 mA
155
mW
AVDD1 = AVDD2 = 24 V, AVSS = −15 V, RLOAD =
1 kΩ, IOUT = 20 mA
550
mW
AVDD1 = AVDD2 = 24 V, AVSS = −15 V, RLOAD =
0 Ω, IOUT = 20 mA
1 The long-term stability specification is noncumulative. The drift in subsequent 1000 hour periods is significantly lower than in the first 1000 hour period.
2 Guaranteed by design and characterization. Not production tested.
3 See the Current Output section for more information on the internal and external RSET resistors.
4 The AD5413 is factory calibrated with an external 2.5 V reference connected to REFIN.
5 Production tested to AVDD1 = 30 V and AVSS = −20 V.
6 AIDD1, AIDD2, and AISS are the currents of the AVDD1, AVDD2, and AVSS supplies, respectively.
AC PERFORMANCE CHARACTERISTICS
AVDD1 = +15 V, AVDD2 = +5 V, AVSS = −15 V, VLOGIC = +1.71 V to +5.5 V, AGND = DGND = REFGND = 0 V, REFIN = +2.5 V external,
RLOAD = 1 kΩ and CLOAD = 220 pF for voltage output, and RLOAD = 300 Ω for current output. All specifications at TA = −40°C to +105°C,
TJ < 125°C, unless otherwise noted.
Table 2.
Parameter1
Min
Typ
Max
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Voltage Output
Output Voltage Settling Time
12
20
μs
10 V step to ±0.03% FSR
15
μs
100 mV step to 1 LSB (14-bit LSB)
Slew Rate
3
V/μs
Digital slew rate control disabled
Power-On Glitch Energy
25
nV-sec
Digital-to-Analog Glitch Energy
7
nV-sec
Glitch Impulse Peak Amplitude
25
mV
Digital Feedthrough
2
nV-sec
Output Noise
0.2
LSB p-p
14-bit LSB, 0.1 Hz to 10 Hz bandwidth
Output Noise Spectral Density
185
nV/√Hz
Measured at 10 kHz, midscale output
AC PSRR
70
dB
200 mV, 50 Hz, and 60 Hz sine waves superimposed on the
power supply voltage
Current Output
Output Current Settling Time
15
μs
To 0.1% FSR
Output Noise
0.2
LSB p-p
14-bit LSB, 0.1 Hz to 10 Hz bandwidth
Output Noise Spectral Density
0.8
nA/√Hz
Measured at 10 kHz, midscale output
AC PSRR
80
dB
200 mV, 50 Hz, and 60 Hz sine waves superimposed on the
power supply voltage
1 Guaranteed by design and characterization. Not production tested.



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