PCF8545ATTA datasheet(36/68 Pages) NXP

36 / 68 page

NXP Semiconductors

PCF8545

Universal LCD driver for multiplex rates up to 1:8

Bit

Symbol

Value

Description

10, 11

unused

4 to 0

unused

Table 24. Control byte description...continued

013aaa461

not relevant

RS[1:0]

MSB

LSB

Figure 25. Control byte format

8.2 I2C-bus interface

The I2C-bus is for bidirectional, two-line communication between different ICs or

modules. The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both

lines must be connected to a positive supply via a pull-up resistor when connected to the

output stages of a device. Data transfer may be initiated only when the bus is not busy.

8.2.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must

remain stable during the HIGH period of the clock pulse as changes in the data line at

this time is interpreted as a control signal (see Figure 26).

mba607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Figure 26. Bit transfer

8.2.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy.

A HIGH-to-LOW change of the data line, while the clock is HIGH, is defined as the

START condition (S).

A LOW-to-HIGH change of the data line, while the clock is HIGH, is defined as the STOP

condition (P).

The START and STOP conditions are shown in Figure 27.

PCF8545

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 4 October 2021

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