LTC7000ARMSEPBF datasheet(9/30 Pages) AD

9 / 30 page

LTC7000A

Rev. 0

For more information www.analog.com

PIN FUNCTIONS

RUN (Pin 1/NA): Run Control Input. A voltage on this pin

above 1.21V enables normal operation. Forcing this pin

below 0.7V shuts down the LTC7000A, reducing quies-

cent current to approximately 1µA. Optionally connect

to the input supply through a resistive divider to set the

undervoltage lockout.

VIN (Pin 2/Pin 1): Main Supply Pin. A bypass capacitor

with a minimum value of 0.1µF should be tied between

this pin and GND.

VCC (Pin 3/Pin 3): Output of internal LDO and power sup-

ply for gate drivers and internal circuitry. Decouple this pin

to GND with a minimum 1.0µF low ESR ceramic capacitor.

Do not use the VCC pin for any other purpose. VCC can

be overdriven from an external high efficiency source for

high frequency switching applications that require higher

power delivered to the external MOSFET. Do not connect

VCC to a voltage greater than VIN.

VCCUV (Pin 4/Pin 5): VCC Supply Undervoltage Lockout.

A resistor on this pin sets the reference for the Gate Drive

undervoltage lockout. The voltage on this pin in the range

of 0.4V to 1.5V is multiplied by 7 to be the undervoltage

lockout for the Gate Drive (VCC pin). Short to ground to

set the minimum gate drive UVLO of 3.5V. Leave open to

set gate drive UVLO to 7.0V

FAULT (Pin 5/Pin 6): Open Drain Fault Output. This pin

pulls low after the voltage on the TIMER pin has reached

the fault threshold of 1.3V. It indicates the pass transistor

is about to turn off due to an overcurrent condition. The

typical pull-down impedance is 200Ω. The FAULT pin does

not go to a high-impedance state until the overcurrent

condition and the TIMER cooldown period expire. If the

TIMER pin is pulled above 3.5V, the TIMER function is

disabled. In this state this pin pulls low when the VTGUP-TS

signal is driven high.

TIMER (Pin 6/Pin 7): Fault Timer Input. A timing capaci-

tor, CT, from the TIMER pin to GND sets the times for fault

warning, fault turn off and retry periods (see Applications

Information). When the TIMER pin is connected to a volt-

age higher than 3.5V, an overcurrent condition will immedi-

ately pull the TGDN pin to TS. TGUP will not go high again

until the fault condition is reset by the INP pin going low

and then back high.

INP (Pin 7/Pin 8): Input Signal. CMOS compatible input

reference to GND that sets the state of TGDN and TGUP

pins (see Applications Information). INP has an internal

1MΩ pull-down to GND to keep TGDN pulled to TS during

startup transients.

OVLO (Pin 8/NA): Overvoltage Lockout Input. Connect

to the input supply through a resistor divider to set the

overvoltage lockout level. A voltage on this pin above

1.21V causes TGDN to be pulled to TS. Normal operation

resumes when the voltage on this pin decreases below

1.11V. Triggering an OVLO causes a fault condition. OVLO

should be tied to GND when not used.

ISET (Pin 9/NA): Current Trip Threshold Set. A resistor

on this pin to GND sets the peak current threshold. The

voltage on this pin (internally clamped between 0.4V and

1.5V) is divided by 20 to be the current comparator ref-

erence. Short to GND for minimum peak current (20mV

ΔVTH). Leave open for an accurate peak current (30mV

ΔVTH).

IMON (Pin 10/NA): Current Monitor. The voltage on this

pin with respect to GND represents the voltage across

the sense resistor multiplied by 20. The range on this pin

is 0V to 1.5V.

TGDN (Pin 11/Pin 9): High Current Gate Driver Pull-Down.

This pin pulls down to TS. For the fastest turn-off, tie this

pin directly to the gate of the external high side MOSFET.

(LTC7000A/LTC7000A-1)

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