CY22313
Document #: 38-07434 Rev. *E
Page 4 of 9
Switching Characteristics[3]
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
FPPM
Frequency Error
Part to Part, does not include PCB variation[8]
±5
±10
PPM
Over commercial temperature range[9]
±2
±5
PPM
DC
Output Duty Cycle
Duty cycle for all outputs, measured at VDD/2
45
50
55
%
t3_54, 2.5
54MOUT Rising Edge Slew Rate 20% to 80% of VDD54, VDD54 = 2.5V
0.75
1.2
4.0
V/ns
t3_54, 1.675 54MOUT Rising Edge Slew Rate 20% to 80% of VDD54, VDD54 = 1.675V
0.35
0.5
2.5
V/ns
t4_54, 2.5
54MOUT Falling Edge Slew Rate 80% to 20% of VDD54, VDD54 = 2.5V
0.75
1.2
4.0
V/ns
t4_54, 1.675 54MOUT Falling Edge Slew Rate 80% to 20% of VDD54, VDD54 = 1.675V
0.35
0.5
2.5
V/ns
tCR, tCF
CLK/CLKB Rise and Fall Times
20% to 80% of output voltage
160
400
ps
tCR-CF
CLK/CLKB Rise and Fall
Difference[10]
20% to 80% of output voltage
100
ps
t5
Lock Time[11]
PLL lock time from power-up
1.0
3.0
ms
Phase Noise Specifications
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
Phase Noise
54 MHz at 10-kHz offset
–95
dBc
Phase Noise
53.946 MHz at 10-kHz offset
–92
dBc
Jitter Specifications[3]
Parameter
Description
Conditions
Typ.
Max.
Unit
t6_LCLK
LCLK Jitter[12]
Cycle-Cycle Jitter – 9.216 MHz
250
ps
t6_54, 2.5
54MOUT Jitter[12]
Cycle-Cycle Jitter – 54 MHz, VDD = 2.5V
150
ps
Cycle-Cycle Jitter – 53.946 MHz, VDD = 2.5V
150
ps
t6_54, 1.675
Cycle-Cycle Jitter – 54 MHz, VDD = 1.675V
250
ps
Cycle-Cycle Jitter – 53.946 MHz, VDD = 1.675V
250
ps
t7_LCLK
LCLK 1000 Cycle Jitter[13]
1000 Cycle Jitter – 9.216 MHz
250
ps
t7_54
54MOUT 1000 Cycle Jitter[13]
1000 Cycle Jitter – 54 MHz,
400
ps
1000 Cycle Jitter – 53.946 MHz,
400
ps
t8
CLK/CLKB 1–6 Cycle Jitter[14]
Cycle-Cycle Jitter, 1–6 Cycles, 400 MHz
50
ps
Cycle-Cycle Jitter, 1–6 Cycles, 300 MHz
70
ps
t9
CLK/CLKB Long-term Jitter[15]
Long-term Jitter, 400 MHz
300
ps
Long-term Jitter, 300 MHz
400
ps
t10
CLK/CLKB Duty Cycle Error[16]
Cycle-Cycle Duty Cycle Error, 400 MHz
50
ps
Cycle-Cycle Duty Cycle Error, 300 MHz
70
ps
Notes:
8.
Tested across three lots on same board, PCB boards can vary more than ± 5 PPM.
9.
Crystal should not be heated for this test, only IC.
10. Measured on same pin of a single device.
11. Lock Time shown in Figure 2.
12. LCLK and 54MOUT Cycle-Cycle Jitter shown in Figure 3.
13. LCLK and 54MOUT 1000 Cycle Jitter shown in Figure 4.
14. CLK/CLKB 1-6 Cycle Jitter specification is absolute value of worst case deviation, and is shown in Figure 5 and Figure 6.
15. CLK/CLKB Long Term Jitter shown in Figure 7.
16. CLK/CLKB Duty Cycle Error shown in Figure 8.
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