SPC58EE80C3 datasheet(58/154 Pages) STMICROELECTRONICS

58 / 154 page

Electrical characteristics

SPC58EEx, SPC58NEx

58/154

DS11646 Rev 4

3.12.4

S/D ADC electrical specification

The SDn ADCs are Sigma Delta 16-bit analog-to-digital converters with 333666 Ksps

maximum output rate.

Note:

The functional operating conditions are given in the DC electrical specifications. Absolute

maximum ratings are stress ratings only, and functional operation at the maxima is not

guaranteed. Stress beyond the listed maximum may affect device reliability or cause

permanent damage to the device.

S/D ADC is functional in the range 3.0 V < VDD_HV_ADV < 4.0 V and

3.0 V < VDD_HV_ADR_D < 4.0 V, but precision of conversion is not guaranteed.

4. All channels of all SAR-ADC12bit and SAR-ADC10bit are impacted with same degradation, independently from the ADC

and the channel subject to current injection.

5. TUE is granted with injection current within the range defined in Table 26, for parameters classified as T and D.

6. DNL is granted with injection current within the range defined in Table 26, for parameters classified as T and D.

Table 29. SDn ADC electrical specification

Symbol

Parameter

Conditions

Value

Unit

Min

Typ

Max

VIN_PK2PK(1)

Input range peak to

peak

VIN_PK2PK =VINP(2)

–VINM(3)

Single ended

VINM =VSS_HV_ADR_D

VDD_HV_ADR_D/GAIN

Single ended

VINM =0.5*VDD_HV_ADR

GAIN = 1

±0.5*VDD_HV_ADR_D

Single ended

VINM =0.5*VDD_HV_ADR

GAIN = 2,4,8,16

±VDD_HV_ADR_D/GAIN

Differential,

0< VIN <

VDD_HV_IO_MAIN

±VDD_HV_ADR_D/GAIN

fADCD_M

SR P

S/D modulator input

Clock 3

TJ < 150 °C

14.4

MHz

fIN

SR P

Input signal

frequency

—0.01

—

75(4)

kHz

fADCD_S

SR D

Output conversion

rate

TJ < 150 °C

—

333

ksps

—

CC D Oversampling ratio

Internal modulator

—

256

—

External modulator

—

256

—

RESOLUTION CC D

S/D register

resolution(5)

2’s complement

notation

bit

GAIN

SR D ADC gain

Defined via

ADC_SD[PGA] register.

Only integer powers of

2 are valid gain values.

1—

—

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