ADP165ACPZN-1.2-R7 datasheet(15/23 Pages) AD

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Data Sheet

ADP165/ADP166

APPLICATIONS INFORMATION

CAPACITOR SELECTION

Output Capacitor, COUT

The ADP165/ADP166 are designed for operation with small,

space-saving ceramic capacitors, but function with most

commonly used capacitors as long as care is taken with regard

to the ESR value. The ESR of the output capacitor affects

stability of the LDO control loop. A minimum of 1 µF

capacitance with an ESR of 1 Ω or less is recommended to

ensure stability of the ADP165/ADP166. Transient response to

changes in load current is also affected by output capacitance.

Using a larger value of output capacitance improves the transient

response of the ADP165/ADP166 to large changes in load

current. Figure 36 and Figure 37 show the transient responses

for output capacitance values of 1 µF and 10 µF, respectively.

CH1 100mA Ω CH2 200mV

M200µs

A CH1

62mA

T 10.40%

LOAD CURRENT

VOUT

Figure 36. Output Transient Response, COUT = 1 µF,

CH1 = Load Current, CH2 = VOUT

CH1 100mA Ω CH2 200mV

M200µs

A CH1

74mA

T 10.00%

LOAD CURRENT

VOUT

Figure 37. Output Transient Response, COUT = 10 µF,

CH1 = Load Current, CH2 = VOUT

Input Bypass Capacitor, CIN

Connecting a 1 µF capacitor from VIN to GND reduces the

circuit sensitivity to the PCB layout, especially when long input

traces or high source impedance are encountered. If an output

capacitance of greater than 1 µF is required, increase the input

capacitor to match it.

Input and Output Capacitor Properties

Any good quality ceramic capacitors can be used with the

ADP165/ADP166, as long as they meet the minimum

capacitance and maximum ESR requirements. Ceramic

capacitors are manufactured with a variety of dielectrics, each

with different behavior over temperature and applied voltage.

Capacitors must have a dielectric adequate to ensure the minimum

capacitance over the necessary temperature range and dc bias

conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V

or 10 V are recommended. Y5V and Z5U dielectrics are not

recommended due to their poor temperature and dc bias

characteristics.

Figure 38 depicts the capacitance vs. voltage bias characteristic

of a 0402, 1 µF, 10 V, X5R capacitor. The voltage stability of a

capacitor is strongly influenced by the capacitor size and voltage

rating. In general, a capacitor in a larger package or higher voltage

rating exhibits better stability. The temperature variation of the X5R

dielectric is about ±15% over the −40°C to +85°C temperature

range and is not a function of package or voltage rating.

1.2

1.0

0.8

0.6

0.4

0.2

VOLTAGE

Figure 38. Capacitance vs. Voltage Bias Characteristic

Use Equation 1 to determine the worst-case capacitance accounting

for capacitor variation over temperature, component tolerance,

and voltage.

CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL)

(1)

where:

CBIAS is the effective capacitance at the operating voltage.

TEMPCO is the worst-case capacitor temperature coefficient.

TOL is the worst-case component tolerance.

In this example, the worst-case temperature coefficient (TEMPCO)

over the −40°C to +85°C range is 15% for an X5R dielectric. The

tolerance of the capacitor (TOL) is 10%, and CBIAS is 0.94 µF at

1.8 V, as shown in Figure 38.

Substituting these values in Equation 1 yields

CEFF = 0.94 µF × (1 − 0.15) × (1 − 0.1) = 0.719 µF

Rev. A | Page 15 of 23

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