STM32WLE4JC datasheet(124/146 Pages) STMICROELECTRONICS

124 / 146 page

Electrical characteristics

STM32WLE5/E4xx

124/146

DS13105 Rev 9

Figure 26. 12-bit buffered/non-buffered DAC

IDDA(DAC)

DAC consumption from

VDDA

DAC output

buffer ON

No load, middle

code (0x800)

315

500

µA

No load, worst code

(0xF1C)

450

670

DAC output

buffer OFF

No load, middle

code (0x800)

0.2

Sample and hold mode, CSH =

100 nF

315 x

Ton/(Ton

+Toff)(4)

670 x

Ton/(Ton

+Toff)(4)

IDDV(DAC)

DAC consumption from

VREF+

DAC output

buffer ON

No load, middle

code (0x800)

185

240

µA

No load, worst code

(0xF1C)

340

400

DAC output

buffer OFF

No load, middle

code (0x800)

155

205

Sample and hold mode, buffer ON,

CSH = 100 nF, worst case

185 x

Ton/(Ton

+Toff)(4)

400 x

Ton/(Ton

+Toff)(4)

Sample and hold mode, buffer OFF,

CSH = 100 nF, worst case

155 x

Ton/(Ton

+Toff)(4)

205 x

Ton/(Ton

+Toff)(4)

1. Guaranteed by design.

2. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).

3. Refer to Table 72: I/O static characteristics.

4. Ton is the Refresh phase duration. Toff is the Hold phase duration. Refer to the reference manual for more details.

Table 84. DAC characteristics(1) (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

MSv47959V2

12-bit

digital-to-analog

converter

Buffered/non-buffered DAC

DAC_OUTx

RLOAD

CLOAD

Buffer

(1)

(1) The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads

directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in

the DAC_CR register.

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