STM32WL55JC datasheet(18/147 Pages) STMICROELECTRONICS

18 / 147 page

Functional overview

STM32WL55/54xx

18/147

DS13293 Rev 2

3.6

Security memory management

The devices contain many security blocks both for the sub-GHz MAC layer and the Host

application, such as:

•

securable RNG

•

customer keys storage

•

secure Flash memory partition for CPU2 only access

•

secure SRAM partition, that can be accessed only by CPU2

•

securable sub-GHz radio sub-system

•

securable DMA channels

•

securable AES: 128-and 256-bit AES, supporting ECB, CBC, CTR, GCM, GMAC and

CCM chaining modes

•

securable PKA:

–

modular arithmetic including exponentiation with maximum modulo size of

3136 bits

–

elliptic curves over prime field scalar multiplication, ECDSA signature, ECDSA

verification with maximum modulo size of 521 bits

•

cyclic redundancy check calculation unit (CRC)

3.7

Boot modes

At startup, BOOT0 pin and BOOT1 option bit are used to select one of the following boot

options:

•

Boot from user Flash memory

•

Boot from boot system memory (where embedded bootloader is located)

•

Boot from embedded SRAM

•

Boot from system memory (where the embedded SFI is located)

The bootloader makes possible to download code from USART or SPI.

If the boot selection uses the BOOT0 pin to boot from the main Flash memory, but the first

Flash memory location is found empty, the Flash empty check mechanism forces boot from

the system memory (containing the embedded bootloader). Then, due to the bootloader

activation, some of the GPIOs are reconfigured from the high-Z state. Refer to the

application note STM32 microcontroller system memory boot mode (AN2606) for more

details concerning the bootloader and GPIOs configuration.

This feature can be disabled by configuring the option bytes (instead of BOOT0 pin) to force

boot from the main Flash memory (nSWBOOT0 = 0, nBOOT0 = 1).

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