ADP1765

Data Sheet

Rev. A | Page 4 of 20

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

Threshold

152

°C

Hysteresis

16

°C

POWER-GOOD (PG) OUTPUT

Output Voltage Threshold

Falling

−6.2

%

Rising

−3.5

%

Output Voltage Low

0.3

V

Leakage Current

0.01

1

µA

Delay

0.75

ms

PRECISION EN INPUT

Logic Input Voltage

High

0.60

0.65

0.69

V

Low

0.55

0.60

0.65

V

Input Logic Hysteresis

50

mV

Input Leakage Current

0.01

1

µA

Input Delay Time

100

µs

UNDERVOLTAGE LOCKOUT

UVLO

Input Voltage

Rising

1.00

1.06

V

Falling

0.85

0.93

V

Hysteresis

70

mV

1

Guaranteed by characterization but not production tested.

2

Based on an endpoint calculation using 100 mA and 5 A loads.

3

Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage, which applies only for output

voltages above 1.1 V.

4

5

Current-limit threshold is the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 1.0 V output voltage

is defined as the current that causes the output voltage to drop to 90% of 1.0 V, or 0.9 V.

INPUT AND OUTPUT CAPACITOR: RECOMMENDED SPECIFICATIONS

Table 3.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

Input

14.5

22

µF

Output

14.5

22

µF

Regulator

0.7

1

µF

Reference

0.07

1

µF

CAPACITOR EQUIVALENT SERIES RESISTANCE (ESR)

0.2

Ω

0.5

Ω

2

Ω

1

The minimum input and output capacitance must be >14.5 µF over the full range of the operating conditions. Consider the full range of the operating conditions in

the application during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended. Y5V and Z5U

capacitors are not recommended for use with any LDO.