PI6C410M datasheet(19/21 Pages) PERICOM

19 / 21 page

PS8736C

12/19/05

PI6C410M/410MA

Clock Generator for Intel

PCI Express Mobile Chipset

AC Electrical Characteristics (VDD = 3.3±5%, VDD_A = 3.3±5%)

Symbol

Outputs

Parameters

Min.

Max. Units Notes

Trise / Tfall

CPU, SRC, DOT

Rise and fall Time

(measured between 0.175V to 0.525V)

175

700

1,2

Trise / Tfall

PCI/PCIF, REF

Rise and fall Time

(measured between 0.8V to 2.0V)

0.5

2.0

Trise / Tfall

USB

Rise and fall Time

(measured between 0.8V to 2.0V)

1.0

2.0

ΔTrise / ΔTfall

CPU, SRC, DOT

Rise and fall Time Variation

125

1, 2

Tskew

CPU0, CPU1

CPU – CPU Skew

100

1,3,6

Tskew

CPU2

CPU – CPU Skew

200

Tskew

SRC

SRC – SRC Skew

250

Tskew

PCI/PCIF, REF

PCI – PCI Skew / REF - REF Skew (measured at

1.5V)

500

Tjitter

CPU0, CPU1

Cycle – Cycle Jitter

1, 3

Tjitter

CPU2

Cycle – Cycle Jitter

125

Tjitter

SRC

Cycle – Cycle Jitter

125

Tjitter

DOT

Cycle – Cycle Jitter

250

Tjitter

PCI/PCIF

Cycle – Cycle Jitter (measured at 1.5V)

500

Tjitter

USB

Cycle – Cycle Jitter (measured at 1.5V)

350

Tjitter

REF

Cycle – Cycle Jitter (measured at 1.5V)

1000

VHIGH

CPU, SRC, DOT

Voltage HIGH including overshoot

660

1150

1, 2

VLOW

CPU, SRC, DOT

Voltage LOW including undershoot

-300

Vcross

CPU, SRC, DOT

Absolute crossing poing voltages

250

550

∆

Vcross

CPU, SRC, DOT

Total variation of Vcross over all edges

140

TDC

CPU, SRC, DOT

Duty-Cycle

1,3,6

TDC

REF, USB, PCI/PCIF Duty-Cycle (measured at 1.5V)

4, 5

Tstable

All clock stabilization from power-up

<1.8

Fig 2

Tdrive

Differential output enable after PwrDwn de-asser-

tion

300

Pwrdwn

Trise / Tfall

Power down rise and fall time

5.0

Pwrdwn

Notes:

1. Test configuration is Rs = 33.2Ω, Rp = 49.9Ω, and CL = 2pF.

2. Single-Ended measurement.

3. Differential measurement.

4. PCI, PCIF, and REF CL(min) = 10pF, CL(max) = 30pF.

5. USB CL(min) = 10pF, CL(max) = 20pF.

6. CPU measured at 133 MHz.

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