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PCA9306AMUTCG bảng dữ liệu(PDF) 5 Page - ON Semiconductor

tên linh kiện PCA9306AMUTCG
Giải thích chi tiết về linh kiện  Dual Bidirectional I2C-bus and SMBus Voltage-Level Translator
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nhà sản xuất  ONSEMI [ON Semiconductor]
Trang chủ  http://www.onsemi.com
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PCA9306AMUTCG bảng dữ liệu(HTML) 5 Page - ON Semiconductor

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Table 5. DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions
TA = −555C to +1255C
Unit
Min
Typ
(Note 8)
Max
VIK
Input Clamping Voltage
II = −18 mA; VI(EN) = 0 V
−1.2
V
IIH
High−Level Input Current
VI = 5 V; VI(EN) = 0 V
5
mA
Ci(EN)
EN Pin Input Capacitance
VI = 3 V or 0 V
7.1
pF
Ci/O(off)
OFF−State I/O Pin Capacitance
SCLn, SDAn
VO = 3 V or 0 V; VI(EN) = 0 V
4
6
pF
Ci/O(on)
ON−State I/O Pin Capacitance
SCLn, SDAn
VO = 3 V or 0 V;
VI(EN) = 3 V
9.3
12.5
pF
RON
ON−State Resistance(2)(3) SCLn, SDAn
VI = 0 V; IO = 64 mA
VI(EN) = 4.5 V
VI(EN) = 3 V
VI(EN) = 2.3 V
VI(EN) = 1.5 V
2.4
3.0
3.8
9.0
5.0
6.0
8.0
20
W
VI = 2.4 V; IO = 15 mA
VI(EN) = 4.5 V
VI(EN) = 3 V
4.8
46
7.5
80
VI = 1.7 V; IO = 15 mA
VI(EN) = 2.3 V
40
80
8. All typical values are at TA = 25°C.
9. Measured by the voltage drop between the SCL1 and SCL2, or SDA1 and SDA2 terminals at the indicated current through the switch.
ON−state resistance is determined by the lowest voltage of the two terminals.
10.Guaranteed by design.
Table 6. AC ELECTRICAL CHARACTERISTICS (Translating Down) − Values Guaranteed by Design
Symbol
Parameter
Test Condition
Load
Condition
TA = −555C to +1255C
Unit
Min
Max
SEE FIGURE 4 LOAD SWITCH AT S2 POSITION
tPLH
Low−to−High Propagation
Delay, from (input) SCL2 or
SDA2 to (output) SCL1 or
SDA1
VI(EN) = 3.3 V; VIH = 3.3 V;
VIL = 0 V; VM = 1.15 V
CL = 15 pF
0
0.6
ns
CL = 30 pF
0
1.2
CL = 50 pF
0
2.0
tPHL
High−to−Low Propagation
Delay, from (input) SCL2 or
SDA2 to (output) SCL1 or
SDA1
CL = 15 pF
0
0.75
CL = 30 pF
0
1.5
CL = 50 pF
0
2.0
tPLH
Low−to−High Propagation
Delay, from (input) SCL2 or
SDA2 to (output) SCL1 or
SDA1
VI(EN) = 2.5 V; VIH = 2.5 V;
VIL = 0 V; VM = 0.75 V
CL = 15 pF
0
0.6
ns
CL = 30 pF
0
1.2
CL = 50 pF
0
2.0
tPHL
High−to−Low Propagation
Delay, from (input) SCL2 or
SDA2 to (output) SCL1 or
SDA1
CL = 15 pF
0
0.75
CL = 30 pF
0
1.5
CL = 50 pF
0
2.5



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