PDU17F-2 datasheet(5/5 Pages) DATADELAY

tên linh kiện	PDU17F-2

Giải thích chi tiết về linh kiện	7-BIT PROGRAMMABLE DELAY LINE (SERIES PDU17F)

PDF	5 Pages

Scroll/Zoom	100%

nhà sản xuất	DATADELAY [Data Delay Devices, Inc.]

Trang chủ	http://www.datadelay.com

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5 / 5 page

PDU17F

Doc #97005

DATA DELAY DEVICES, INC.

1/14/97

3 Mt. Prospect Ave. Clifton, NJ 07013

DELAY LINE AUTOMATED TESTING

TEST CONDITIONS

INPUT:

OUTPUT:

Ambient Temperature: 25

± 3oC

Load:

1 FAST-TTL Gate

Supply Voltage (Vcc): 5.0V

± 0.1V

Cload:

5pf

± 10%

Input Pulse:

High = 3.0V

± 0.1V

Threshold:

1.5V (Rising & Falling)

Low = 0.0V

± 0.1V

Source Impedance:

Ω Max.

Rise/Fall Time:

3.0 ns Max. (measured

between 0.6V and 2.4V )

Pulse Width:

PWIN = 1.5 x Total Delay

Period:

PERIN = 4.5 x Total Delay

NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.

OUT

TRIG

REF

TRIG

Test Setup

DEVICE UNDER

TEST (DUT)

TIME INTERVAL

COUNTER

PULSE

GENERATOR

COMPUTER

SYSTEM

PRINTER

Timing Diagram For Testing

TDAR

TDAF

PERIN

PWIN

TRISE

TFALL

0.6V

1.5V

2.4V

1.5V

VIH

VIL

VOH

VOL

INPUT

SIGNAL

OUTPUT

SIGNAL

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