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TMUX7308FRRPR bảng dữ liệu(PDF) 38 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  TMUX730xF 짹60-V Fault-Protected, 8:1 and Dual 4:1 Multiplexers with Latch-Up Immunity and 1.8-V Logic
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9.4.2 Fault Mode
The TMUX7308F and TMUX7309F enter into the Fault mode when any of the input signals on the source
(Sx) pins exceed VDD or VSS by a threshold voltage VT. Under the overvoltage condition, the switch input
experiencing the fault automatically turns OFF regardless of the logic status, and the source pin becomes high
impedance with a negligible amount of leakage current flowing through the switch. When the fault channel is
selected by the logic control, the drain pin (D or Dx) is pulled to the supply that was exceeded through a 40 kΩ
internal resistor.
The overvoltage protection is provided only for the source (Sx) input pins. The drain (D or Dx) pin, if used as a
signal input, must stay in between VDD and VSS at all times since no overvoltage protection is implemented on
the drain pin.
9.4.3 Truth Tables
Table 9-1 shows the truth tables for the TMUX7308F.
Table 9-1. TMUX7308F Truth Table
EN
A2
A1
A0
Selected Source Connected to Drain Pin
(D)
0
X(1)
X(1)
X(1)
All sources are off (HI-Z)
1
0
0
0
S1
1
0
0
1
S2
1
0
1
0
S3
1
0
1
1
S4
1
1
0
0
S5
1
1
0
1
S6
1
1
1
0
S7
1
1
1
1
S8
(1)
"X" means "do not care."
Table 9-2 shows the truth tables for the TMUX7309F.
Table 9-2. TMUX7309F Truth Table
EN
A1
A0
Selected Source Connected to Drain Pins (DA, DB)
0
X(1)
X(1)
All sources are off (HI-Z)
1
0
0
S1A and S1B
1
0
1
S2A and S2B
1
1
0
S3A and S3B
1
1
1
S4A and S4B
(1)
"X" means "do not care."
If unused, Ax pins must be tied to GND in order to ensure the device does not consume additional current as
highlighted in Implications of Slow or Floating CMOS Inputs. Unused signal path inputs (Sx or Dx) should be
connected to GND.
TMUX7308F, TMUX7309F
SCDS403B – FEBRUARY 2021 – REVISED DECEMBER 2021
www.ti.com
38
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Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMUX7308F TMUX7309F



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