AD9887APCB datasheet(3/44 Pages) AD | Dual Interface for Flat Panel Displays

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AD9887APCB bảng dữ liệu(PDF) 3 Page - Analog Devices

tên linh kiện	AD9887APCB

Giải thích chi tiết về linh kiện	Dual Interface for Flat Panel Displays

PDF	44 Pages

Scroll/Zoom	100%

nhà sản xuất	AD [Analog Devices]

Trang chủ	http://www.analog.com

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TABLE INDEX (continued)

Table XXIX. Sync Detect Polarity Settings . . . . . . . . . . . . . 35

Table XXX. HSYNC Detection Results . . . . . . . . . . . . . . . 36

Table XXXI. Sync-on-Green Detection Results . . . . . . . . . 36

Table XXXII. VSYNC Detection Results . . . . . . . . . . . . . . 36

Table XXXIII. Digital Interface Clock Detection Results . . 36

Table XXXIV. Active Interface Results . . . . . . . . . . . . . . . . 36

Table XXXV. Active HSYNC Results . . . . . . . . . . . . . . . . . 36

Table XXXVI. Active VSYNC Results . . . . . . . . . . . . . . . . 37

Table XXXVII. Active Interface Override Settings . . . . . . . 37

Table XXXVIII. Active Interface Select Settings . . . . . . . . . 37

Table XXXIX. Active Hsync Override Settings . . . . . . . . . . 37

Table XL. Active HSYNC Select Settings . . . . . . . . . . . . . . 37

Table XLI. Active VSYNC Override Settings . . . . . . . . . . . 37

Table XLII. Active VSYNC Select Settings . . . . . . . . . . . . . 37

Table XLIII. COAST Select Settings . . . . . . . . . . . . . . . . . 37

Table XLIV. Power-Down Settings . . . . . . . . . . . . . . . . . . . 37

Table XLV. Scan Enable Settings . . . . . . . . . . . . . . . . . . . . 38

Table XLVI. Coast Input Polarity Override Settings . . . . . . 38

Table XLVII. HSYNC Input Polarity Override Settings . . . 38

Table XLVIII. Detected HSYNC Input Polarity Status . . . 38

Table XLIX. Detected VSYNC Input Polarity Status . . . . . 38

Table L. Detected Coast Input Polarity Status . . . . . . . . . . 38

Table LI. 4:2:2 Input/Output Configuration . . . . . . . . . . . . 39

Table LII. 4:2:2 Output Mode Select . . . . . . . . . . . . . . . . . 39

Table LIII. Serial Port Addresses . . . . . . . . . . . . . . . . . . . . 39

Table LIV. Control of the Sync Block Muxes via the Serial

Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

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