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AL4CS211/AL4CS221/AL4CS231/AL4CS241/AL4CS251
AL4CS211/AL4CS221/AL4CS231/AL4CS241/AL4CS251
December 14, 2001
6
5.0 Pin-out Diagram
The AL4CS211/AL4CS221/AL4CS231/AL4CS241/AL4CS251 pin-out diagram is following:
TQFP PACKAGE TOP VIEW
AVERLOGIC
AL4CS2X1
x-xx-xx
xxxx
xxxx
/FF
Q0
Q1
Q2
Q3
/OE
/EF
Q4
16
15
14
13
12
11
10
9
D2
D3
D7
/RS
D8
D4
D5
D6
25
26
27
28
29
30
31
32
13
30
4
1
21
20
14
AVERLOGIC
AL4CS2X1
x-xx-xx
xxxx
xxxx
31
32
2
3
15
16
17
18
19
22
23
24
25
26
27
28
29
12
11
10
9
8
7
6
5
Q2
Q1
Q0
/FF
/EF
Q3
Q4
D6
D5
D4
D3
D8
D2
D7
PLCC PACKAGE TOP VIEW
6.0 Block Diagram
(512, 1k ,2k,
4k, 8k) x9
Memory
Array
Input
Buffer
Output
Buffer
Write Control
Logic
Read Control
Logic
Flag Logic
Write Pointer
Read Pointer
Offset
Regissers
Reset Logic
Input data bus
Output data bus
/OE
WCLK
/WEN1
/LD
/RS
RCLK
/REN1
/FF
/EF
/PAF
/PAE
Figure 1. AL4CS2x1 FIFO Block Diagram
WEN2
/REN2
The internal structure of the AL4CS211/AL4CS221/AL4CS231/AL4CS241/AL4CS251 consists of
Input/Output buffers, Read/Write Control Logic and main (512, 1k, 2k, 4k, 8k) x9 different
configuration memory cell array and state-of-the-art logic design that takes care of addressing and
controlling the read/write data.
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