AD7656BSTZ datasheet(24/25 Pages) AD

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AD7658/AD7657/AD7656

Preliminary Technical Data

Rev. PrI | Page 24 of 25

APPLICATION HINTS

Layout

The printed circuit board that houses the AD7656 should be

designed so the analog and digital sections are separated and

confined to certain areas of the board. This facilitates the use of

ground planes that can be easily separated. Digital and analog

ground planes should be joined in only one place, preferably

underneath the AD7656, or, at least, as close as possible to the

AD7656. If the AD7656 is in a system where multiple devices

require analog to digital ground connections, the connection

should still be made at one point only, a star ground point,

which should be established as close as possible to the AD7656.

It is recommended to avoid running digital lines under the

device as these will couple noise onto the die. The analog

ground plane should be allowed to run under the AD7656 to

avoid noise coupling. Fast switching signals like CONVST or

clocks should be shielded with digital ground to avoid radiating

noise to other sections of the board and should never run near

analog signal paths. Crossover of digital and analog signals

should be avoided. Traces on different but close layers of the

board should run at right angles to each other. This will reduce

the effect of feedthrough through the board.

The power supply lines to the AD7656 should use as large a

trace as possible to provide low impedance paths and reduce

the effect of glitches on the power supply lines. Good

decoupling is also important to lower the supplies impedance

presented to the AD7656 and to reduce the magnitude of the

supply spikes. Decoupling ceramic capacitors, typically 100 nF,

should be placed on all of the power supply pins, power

supplies pins VDD, VSS, AVCC, DVCC, and VDRIVE. The decoupling

capacitors should be placed close to, and ideally right up

against, these pins and their corresponding ground pins.

Additionally, low ESR 10 µF capacitors should be located in the

vicinity of the ADC to further reduce low frequency ripple.

The decoupling capacitors should be close to the ADC and

connected with short and large traces to minimize parasitic

inductances.

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