UCS2113 datasheet(28/62 Pages) MICROCHIP

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UCS2113

DS20005680B-page 28

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6.6

Fault Handling Mechanism

The UCS2113 has two modes for handling faults:

• Latch (latch-upon-fault)

• Auto-recovery (automatically attempt to restore

the Active power state after a fault occurs).

If the SMBus is actively utilized, Auto-Recovery Fault

Handling is the default error handler as determined by

the LATCH_SET bit. Faults include overcurrent,

overvoltage (on VS), undervoltage (on VBUS),

back-voltage (VBUS to VS or VBUS to VDD), discharge

error, and maximum allowable internal die temperature

(TTSD_HIGH) exceeded. Fault conditions also include

the situations when TTSD_LOW die temperature has

been exceeded and any of the following conditions are

met:

• a power switch operates in constant current mode

• PWR_EN1 and/or PWR_EN2 controls transition

from inactive to active.

• it is a power up situation and PWR_EN1 and/or

PWR_EN2 pins are active.

Faults do not include:

• keep-out violations except VBUS_MIN.

•TTSD_LOW die temperature has been exceeded

and any of the following conditions are met:

- the power switch is closed at the time when

TTSD_LOW is reached and it is not in constant

current mode.

- the power switch remains open (PWR_EN1

and/or PWR_EN2 controls are not active).

6.6.1

AUTO-RECOVERY FAULT

HANDLING

When the LATCH_SET bit is low, Auto-Recovery Fault

Handling is used. When an error condition is detected,

the UCS2113 will immediately enter the Error state

and assert the ALERT# pin. Independently from the

host controller, the UCS2113 will wait a preset time

(tCYCLE), check error conditions (tTST), and restore

Active operation if the error condition(s) no longer

exist. If all other conditions that may cause the

ALERT# pin to be asserted have been removed, the

ALERT#

will

released.

Short-Circuit

Auto-Recovery example in Figure 6-6.

FIGURE 6-6:

Error Recovery.

6.6.2

LATCHED FAULT HANDLING

When the LATCH_SET bit is high, latch fault handling

is used. When an error condition is detected, the

UCS2113 will enter the Error power state and assert

the ALERT# (1 or 2) pin. Upon command from the host

controller (by toggling the PWR_EN (1, or 2) pin

control from enabled to disabled or by clearing the

ERR bit via SMBus), the UCS2113 will check error

conditions once and restore Active operation if error

conditions no longer exist. If an error condition still

exists, the host controller is required to issue the

command again to check error conditions.

If the ALERT# pin is asserted and the interrupt status

registers (addresses 03h or 04h) are not read, the

corresponding ALERT# pin remains asserted until the

corresponding PWR_EN pin is toggled.

If the ALERT# pin is asserted and the interrupt status

registers are read, the ALERT# pin will deassert, but

the UCS will remain in error state until the ERR bit is

cleared via SMBus or the PWR_EN pin is toggled.

tTST

VBUS

IBUS

SHORT

applied.

ITEST

tDISCHARGE

ITEST

VTEST

Short Detected. VBUS

discharged. Enter

Error state.

Check short

condition. Short

still present.

Return to Error

State.

Wait tCYCLE.

Check short

condition. Short

removed.

Return to

normal

operation.

tCYCLE

tTST

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