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DLPC4430ZPC bảng dữ liệu(PDF) 37 Page - Texas Instruments

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tên linh kiện DLPC4430ZPC
Giải thích chi tiết về linh kiện  DLPC4430 DLP짰 Display Controller
PDF  49 Pages
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DLPC4430ZPC bảng dữ liệu(HTML) 37 Page - Texas Instruments

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Figure 10-1. PLL Filter Layout
High frequency decoupling is required for both 1.15V and 1.8V PLL supplies and must be provided as close as
possible to each of the PLL supply package pins. It is recommended to place decoupling capacitors under the
package on the opposite side of the board. Use high quality, low-ESR, monolithic, surface mount capacitors.
Typically 0.1µF for each PLL supply is sufficient. The length of a connecting trace increases the parasitic
inductance of the mounting and thus, tracing should be avoided, allowing the via to butt up against the land
itself. Additionally, the connecting trace has to be made as wide as possible. Further improvement can be made
by placing vias to the side of the capacitor lands or doubling the number of vias.
The location of bulk decoupling depends on the system design.
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DLPC4430
DLPS223 – DECEMBER 2021
Copyright © 2021 Texas Instruments Incorporated
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