EDB8164B4PT-1DITF-R datasheet(64/152 Pages) MICRON

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Table 48: PRECHARGE and Auto Precharge Clarification (Continued)

From

Command

To Command

Minimum Delay Between Commands

Unit

Notes

WRITE w/AP

PRECHARGE to same bank as WRITE w/AP

WL + BL/2 + RU(tWR/tCK) + 1

CLK

1, 2

PRECHARGE ALL

WL + BL/2 + RU(tWR/tCK) + 1

CLK

ACTIVATE to same bank as WRITE w/AP

WL + BL/2 + RU(tWR/tCK) + 1 + RU(tRPpb/tCK)

CLK

WRITE or WRITE w/AP (same bank)

Illegal

CLK

WRITE or WRITE w/AP (different bank)

BL/2

CLK

READ or READ w/AP (same bank)

Illegal

CLK

READ or READ w/AP (different bank)

WL + BL/2 + RU(tWTR/tCK) + 1

CLK

PRECHARGE

PRECHARGE to same bank as PRECHARGE

CLK

PRECHARGE ALL

CLK

PRECHARGE

ALL

PRECHARGE

CLK

PRECHARGE ALL

CLK

Notes:

1. For a given bank, the PRECHARGE period should be counted from the latest PRECHARGE

command—either a one-bank PRECHARGE or PRECHARGE ALL—issued to that bank.

The PRECHARGE period is satisfied after tRP, depending on the latest PRECHARGE com-

mand issued to that bank.

2. Any command issued during the specified minimum delay time is illegal.

3. After READ with auto precharge, seamless READ operations to different banks are sup-

ported. After WRITE with auto precharge, seamless WRITE operations to different banks

are supported. READ with auto precharge and WRITE with auto precharge must not be

interrupted or truncated.

REFRESH Command

The REFRESH command is initiated with CS_n LOW, CA0 LOW, CA1 LOW, and CA2

HIGH at the rising edge of the clock. A per-bank REFRESH command is initiated with

CA3 LOW at the rising edge of the clock. The all-bank REFRESH command is initiated

with CA3 HIGH at the rising edge of the clock. A per-bank REFRESH is only supported

in devices with eight banks.

A per-bank REFRESH command (REFpb) performs a per-bank REFRESH operation to

the bank scheduled by the bank counter in the memory device. The bank sequence for

per-bank REFRESH is fixed to be a sequential round-robin: 0-1-2-3-4-5-6-7-0-1-.... The

bank count is synchronized between the controller and the SDRAM by resetting the

bank count to zero. Synchronization can occur upon issuing a RESET command or at

every exit from self refresh.

A bank must be idle before it can be refreshed. The controller must track the bank being

refreshed by the per-bank REFRESH command.

The REFpb command must not be issued to the device until the following conditions

have been met:

• tRFCab has been satisfied after the prior REFab command

• tRFCpb has been satisfied after the prior REFpb command

• tRP has been satisfied after the prior PRECHARGE command to that bank

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

REFRESH Command

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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