PCF85363ATLSLASHAX datasheet(69/86 Pages) NXP

69 / 86 page

NXP Semiconductors

PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I2C-bus

VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = -40 °C to +85 °C; fosc = 32.768 kHz; quartz Rs = 60 kΩ; CL = 7 pF; unless otherwise

specified. All timing values are valid within the operating supply voltage and temperature range and referenced to VIL and

VIH with an input voltage swing of VSS to VDD [1] .

Symbol

Parameter

Conditions

Min

Max

Unit

tHD;DAT

data hold time

tSU;STO

set-up time for STOP

condition

0.6

μs

tVD;DAT

data valid time

0.9

μs

tVD;ACK

data valid

acknowledge time

0.9

μs

tSP

pulse width of

spikes that must be

suppressed by the

input filter

Table 68. I2C-bus characteristics...continued

[1]

A detailed description of the I2C-bus specification is given in [4].

[2]

I2C-bus access time between two STARTs or between a START and a STOP condition to this device must be less than one second.

[3]

A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge the undefined

region of the falling edge of SCL.

[4]

The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This

allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum

specified tf.

SCL

SDA

tHD;STA

tSU;DAT

tHD;DAT

tBUF

tSU;STA

tLOW tHIGH

tVD;ACK

013aaa417

tSU;STO

protocol

START

condition

(S)

bit 7

MSB

(A7)

bit 6

(A6)

bit 0

(R/W)

acknowledge

(A)

STOP

condition

(P)

1/fSCL

tVD;DAT

Figure 41. I2C-bus timing diagram; rise and fall times refer to 30 % and 70 %

PCF85363A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3.1 — 18 June 2021

69 / 86

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