TCS3471 datasheet(20/38 Pages) AMSCO

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[v1-01] 2018-Mar-27

TCS3471 − Register Description

Enable Register (0x00)

The Enable register is used primarily to power the TCS3471

device on and off, and enable functions and interrupts as shown

in Figure 24.

Figure 24:

Enable Register

Note(s):

1. A minimum interval of 2.4 ms must pass after PON is asserted before an RGBC can be initiated.

Reserved

AIEN

WEN

Reserved

AEN

PON

Field

Bits

Description

Reserved

7:5

Reserved. Write as 0.

AIEN

RGBC interrupt enable. When asserted, permits RGBC interrupts to be

generated.

WEN

Wait enable. This bit activates the wait feature. Writing a 1 activates the

wait timer. Writing a 0 disables the wait timer.

Reserved

Reserved. Write as 0.

AEN

RGBC enable. This bit actives the two-channel ADC. Writing a 1 activates

the RGBC. Writing a 0 disables the RGBC.

PON(1)

Power ON. This bit activates the internal oscillator to permit the timers and

ADC channels to operate. Writing a 1 activates the oscillator. Writing a 0

disables the oscillator. During reads and writes over the I²C interface, this

bit is temporarily overridden and the oscillator is enabled, independent of

the state of PON.

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