ADP5135ACPZ-R7 datasheet(23/24 Pages) AD

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Data Sheet

ADP5135

Rev. 0 | Page 23 of 24

PCB LAYOUT GUIDELINES

Poor layout can affect ADP5135 performance, causing EMI and

electromagnetic compatibility (EMC) problems, ground

bounce, and voltage losses. Poor layout can also affect

regulation and stability. A good layout is implemented using the

following guidelines. Also, refer to the ADP5135CP-EVALZ

user guide.



Place the inductor, input capacitor, and output capacitor

close to the IC using short tracks. These components carry

high switching frequencies, and large tracks act as antennas.



Route the output voltage path away from the inductor and

SWx node to minimize noise and magnetic interference.



Maximize the size of ground metal on the component side

to help with thermal dissipation.



Connect VIN1, VIN2, VIN3, and AVIN together close to

the IC using short tracks.



Use a ground plane with several vias connecting to the

component side ground to further reduce noise

interference on sensitive circuit nodes.



For best performance, connect the input capacitors very

close to the pins as follows: place the AVIN capacitor

between the AVIN and AGND pins, place the VIN1

capacitor between the VIN1 and PGND1 pins, place the

VIN2 capacitor between the VIN2 and PGND2 pins, and

place the VIN3 capacitor between VIN3 and PGND3.

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