ADP5041ACPZ-1-R7 datasheet(37/40 Pages) AD

37 / 40 page

Data Sheet

ADP5041

Rev. B | Page 37 of 40

PCB LAYOUT GUIDELINES

Poor layout can affect ADP5041 performance, causing electro-

magnetic interference (EMI) and electromagnetic compatibility

(EMC) problems, ground bounce, and voltage losses. Poor

layout can also affect regulation and stability. A good layout is

implemented using the following guidelines:



Place the inductor, input capacitor, and output capacitor

close to the IC using short tracks. These components carry

high switching frequencies, and large tracks act as antennas.



Route the output voltage path away from the inductor and

SW node to minimize noise and magnetic interference.



Maximize the size of ground metal on the component side

to help with thermal dissipation.



Use a ground plane with several vias connecting to the

component side ground to further reduce noise interference

on sensitive circuit nodes.

SUGGESTED LAYOUT

See Figure 114 for an example layout.

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

1.0

2.0

3.0

5.5

6.0

6.5

AVIN

VIN1

PGND

WDI

VTHR

MODE

AGND

EN2

4.0

5.0

6.0

VOUT3

VOUT1

VOUT2

PPL

7.0

TOP LAYER

PPL

GPL

PPL

VIAS LEGEND:

PPL = POWER PLANE (+4V)

GPL = GROUND PLANE

2ND LAYER

0.5

1.5

2.5

3.5

4.5

5.5

L1–1µH

0603

RFILT

30Ω

0402

C1 – 4.7µF

10V/XR5 0603

EN1

C2–1µF

10V/XR5

0402

ADP5041

C5–2.2µF

6.3V/XR5

0402

C3 – 1µF

10V/XR5

0402

C6 – 2.2µF

6.3V/XR5

0402

C4 – 10µF

6.3V/XR5

0603

Figure 114. Suggested Board Layout

ADP5041ACPZ-1-R7 bảng dữ liệu(PDF) 37 Page - Analog Devices

ADP5041ACPZ-1-R7 bảng dữ liệu(HTML) 37 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

bảng dữ liệu tải về

Link URL