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ML2302 bảng dữ liệu(PDF) 6 Page - OKI electronic componets

tên linh kiện ML2302
Giải thích chi tiết về linh kiện  Recording and Playback LSI with Built-in 2-Bit ADPCM2 Supported FIFO
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ML2302 bảng dữ liệu(HTML) 6 Page - OKI electronic componets

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FEDL2302DIGEST-05
OKI Semiconductor
ML2302
6/24
Pin
(WCSP)
Pin
(TQFP)
Symbol
Type
Description
J3
61
SIOCK
I/O
16-bit serial data transfer clock when external A/D or D/A
converter is used.
J4
58
VCK
I/O
Outputs sampling frequency selected. Input pin when slave
mode is selected.
J7
H7
51
50
XT
XT
I
O
Oscillator connection pins. when external clock is used, input
clock into XT pin and leave
XT pin open. Oscillation stops
during reset or power down mode. Figure (a) shows Oscillation
Equivalent Circuit.
E9
40
RESET
I
When this pin is “L”, the LSI is initialized and AOUT is set to the
GND level.
E8
39
FIFOST
I
When this pin is “L”, EMP, MID, and FULL of playback FIFO can
be monitored. When this pin is “H”, EMP, MID, and FULL of
record FIFO can be monitored.
B3
18
SG
O
Analog circuit signal ground pin. This pin is connected to GND
during reset or power down mode.
A4
C4
22
20
MIN
LIN
I
Inverting input pin for built-in OP amplifier. Non-inverting input
pin is connected to SG (Signal Ground).
B4
A3
21
19
MOUT
LOUT
O
MOUT is the output of internal OP amplifier to MIN, and LOUT
is to LIN.
A5
25
AOUT
O
This is the output of the analog playback waveform.
H6
52
VOXO
O
Voice level detection signal
H8, B2
49, 16
TEST0, 8
I
Pins for testing. Set the pins to “L”.
E3, G8
9, 46
DVDD
—
Digital power supply pin. Insert a minimum 0.1
µF bypass
capacitor between this pin and DGND pin
D7, G5
38, 57
DGND
—
Digital GND pin.
A2, B8
17, 33
AVDD
—
Analog power supply pin. Insert a minimum 0.1
µF bypass
capacitor between this pin and AGND pin.
C5, A8
23, 32
AGND
—
Analog GND pin.
C9, D8
36
35
CB1
CB2
O
This pin is used to connect a capacitor for voltage multiplier
power supply. Insert a 1
µF capacitor between CB1 and CB2.
C8
34
SPVDD
O
Voltage multiplier power supply output pin for speaker amplifier.
Connect a 1
µF capacitor to this pin in order to stabilize the
speaker amplifier circuit.
D9
37
VR
O
Bias output pin for speaker amplifier. Set this pin to the GND
level during reset or power down mode.
A6
26
SPIN
I
Voice signal input pin for speaker amplifier.
B6
27
SPOUT–
O
Speaker amplifier output pin. This pin outputs a signal in
reverse phase to the signal that is input to the SPIN pin.
C6
28
SPOUT+
O
Speaker amplifier output pin. This pin outputs a signal in phase
to the signal that is input to the SPIN pin.
D1, D2,
D3, C1,
C2, B1,
B5
10~15
,24
TEST2 to
7, 9
O
Pins for testing. Leave these pins open.



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