MPC8343ECVRADDB datasheet(10/80 Pages) NXP

10 / 80 page

MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11

Freescale Semiconductor

Power Characteristics

supplies are stable and if the I/O voltages are supplied before the core voltage, there may be a period of

time that all input and output pins will actively be driven and cause contention and excessive current from

3A to 5A. In order to avoid actively driving the I/O pins and to eliminate excessive current draw, apply the

core voltage (VDD) before the I/O voltage (GVDD, LVDD, and OVDD) and assert PORESET before the

power supplies fully ramp up. In the case where the core voltage is applied first, the core voltage supply

must rise to 90% of its nominal value before the I/O supplies reach 0.7 V, see Figure 4.

Figure 4. Power Sequencing Example

I/O voltage supplies (GVDD, LVDD, and OVDD) do not have any ordering requirements with respect to one

another.

Power Characteristics

The estimated typical power dissipation for the MPC8343EA device is shown in Table 4.

Table 4. MPC8343EA Power Dissipation1

1 The values do not include I/O supply power (OV

DD, LVDD, GVDD) or AVDD. For I/O power values, see Table 5.

Core

Frequency

(MHz)

CSB

Frequency

(MHz)

Typical at TJ = 65

Typical2

2 Typical power is based on a voltage of V

DD = 1.2 V, a junction temperature of TJ = 105°C, and a Dhrystone benchmark

application.

3 Thermal solutions may need to design to a value higher than typical power based on the end application, T

A target, and I/O

power.

Maximum4

4 Maximum power is based on a voltage of V

DD = 1.2 V, worst case process, a junction temperature of TJ = 105°C, and an

artificial smoke test.

Unit

PBGA

266

1.3

1.6

1.8

133

1.1

1.4

1.6

400

266

1.5

1.9

2.1

133

1.4

1.7

1.9

400

200

1.5

1.8

2.0

100

1.3

1.7

1.9

I/O Voltage (GVDD, LVDD, OVDD)

Core Voltage (VDD, AVDD)

90%

0.7 V

Time

Voltage

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