ML2213 datasheet(4/26 Pages) OKI

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FEDL 2213-01

1Semiconductor

ML2213

4/26

PIN DESCRIPTIONS

Symbol

Type

Description

11 (19)

RESET

“L” input to this pin turns the LSI into standby mode. At this point, output from

the AOUT pin rises up to V

DD level, having the LSl initialized internally. By “H”

input to the pin the AOUT output returns to 1/2 V

DD level.

2 (4)

NAR

This pin outputs a signal showing empty/full status of the Phase Address

Latch Resister. “H” level indicates the register is empty, and thus the LSI is

ready to accept serial data input. At powering up, the pin outputs “H level”.

3 (5)

BUSY

Output “L” level while output signal is present either at the AOUT or MD pin.

At powering up, the pin outputs “H” level.

4 (6)

Music output pin

6 (9)

AOUT

Analog output pin

5 (8)

GND

—

Ground pin

9 (16)

CLK

External clock input pin

12 (20)

Serial clock input pin

13 (21)

Serial data input pin. Input a phrase code corresponding to a phrase address

through this pin.

10 (17)

Chip select signal pin. Mask option allows a user to choose either 2-pin (SD

and Sl) interfacing or 3-pin (SD, Sl and

ST) interfacing. When 3-pin inter-

facing is selected, input to the SD and Sl pins is valid while the

ST pin being

held “L”. When 2-pin interfacing is selected, pull this pin down to the GND.

8 (15)

—

Power supply pin. Insert 0.1

µF or larger bypass capacitor between this pin

and the GND pin.

* 14-pin plastic SSOP (24-pin plastic SOP)

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