ADP5065ACBZ-1-R7 datasheet(23/40 Pages) AD

23 / 40 page

Data Sheet

ADP5065

Rev. D | Page 23 of 40

I2C INTERFACE

The ADP5065 includes an I2C-compatible serial interface for

control of the charging and for a readback of system status

registers. The I2C chip address is 0x28 in write mode and 0x29

in read mode.

voltage at the VINx pin falls below the VVIN_OK falling voltage

threshold. The I2C registers are also reset when the battery is

disconnected and VIN is 0 V.

See Figure 34 for an example of the I2C write sequence to a

single register. The subaddress content selects which one of the

five ADP5065 registers is written to first. The ADP5065 sends

an acknowledgement to the master after the 8-bit data byte has

been written. The ADP5065 increments the subaddress

automatically and starts receiving a data byte to the following

Figure 36 shows the I2C read sequence of a single register.

ADP5065 sends the data from the register denoted by the

subaddress and increments the subaddress automatically,

sending data from the next register until the master sends an

I2C stop condition as shown in Figure 37.

SUBADDRESS

CHIP ADDRESS

1010

ADP5065 RECEIVES

DATA

0 = WRITE

MASTER STOP

Figure 34. I2C Single Register Write Sequence

CHIP ADDRESS

SUBADDRESS

ADP5065 RECEIVES

DATA TO REGISTER N

ADP5065 RECEIVES

DATA TO REGISTER N + 1

ADP5065 RECEIVES

DATA TO LAST REGISTER

1010

0 = WRITE

MASTER STOP

Figure 35. I2C Multiple Register Write Sequence

CHIP ADDRESS

SUBADDRESS

CHIP ADDRESS

ADP5065 SENDS DATA

101

0 = WRITE

1 = READ

Figure 36. I2C Single Register Read Sequence

CHIP ADDRESS

SUBADDRESS

CHIP ADDRESS

ADP5065 SENDS

DATA OF REGISTER N

ADP5065 SENDS

DATA OF REGISTER

N + 1

ADP5065 SENDS

DATA OF LAST

101

0 = WRITE

1 = READ

MASTER STOP

Figure 37. I2C Multiple Register Read Sequence

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