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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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SH7041A bảng dữ liệu(PDF) 264 Page - Renesas Technology Corp |
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SH7041A bảng dữ liệu(HTML) 264 Page - Renesas Technology Corp |
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264 / 923 page  226 • Bit 0—DMAC Enable (DE): DE enables operation in the corresponding channel. Bit 0: DE Description 0 Operation of the corresponding channel disabled (initial value) 1 Operation of the corresponding channel enabled Transfer mode is entered if this bit is set to 1 when auto-request is specified (RS3–RS0 settings). With an external request or on-chip module request, when a transfer request occurs after this bit is set to 1, transfer is enabled. If this bit is cleared during a data transfer, transfer is suspended. If the DE bit has been set, but TE = 1, then if the DME bit of the DMAOR is 0, and the NMI or AE bit of the DMAOR is 1, transfer enable mode is not entered. 11.2.5 DMAC Operation Register (DMAOR) The DMAOR is a 16-bit read/write register that specifies the transfer mode of the DMAC Register values are initialized to 0 during power-on reset or in software standby mode. Manual reset does not initialize DMAOR. Bit: 15 14 13 12 11 10 9 8 — — — — — — PR1 PR0 Initial value: — — — — — — 0 0 R/W: R R R R R R R/W R/W Bit: 7 6 5 4 3 2 1 0 — — — — — AE NMIF DME Initial value: — — — — — — 0 0 R/W: R R R R R R/(W)* R/(W)* R Note: * 0 write only is valid after 1 is read at the AE and NMIF bits. • Bits 15–10—Reserved bits: Data are 0 when read. The write value always be 0. |
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