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SH7041A bảng dữ liệu(HTML) 186 Page - Renesas Technology Corp |
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186 / 923 page  148 Table 8.2 Interrupt Sources and DTC Vector Addresses (cont) Source Generator Activating Source DTC Vector Address DTE Bit Transfer Source Transfer Destination Priority SCI0 RXI0 H'00000438–H'00000439 DTED3 RDR0 Arbitrary* 1 High TXI0 H'0000043A–H'0000043B DTED2 Arbitrary* 1 TDR0 SCI1 RXI1 H'0000043C–H'0000043D DTED1 RDR1 Arbitrary* 1 TXI1 H'0000043E–H'0000043F DTED0 Arbitrary* 1 TDR1 BSC CMI H'00000440–H'00000441 DTEE7 Arbitrary* 1 Arbitrary*1 Software Write to DTCSR H'00000400 + DTVEC[7:0] to H'00000401 + DTVEC[7:0] — Arbitrary* 1 Arbitrary*1 Low Notes: *1 External memory, memory-mapped external devices, on-chip memory, on-chip peripheral modules (excluding DMAC and DTC) *2 Excluding A mask products are ADI, A mask products are ADI0. 8.3.4 Register Information Placement Figure 8.5 shows the placement of register information in memory space. The register information start addresses are designated by DTBR for the upper 16 bits, and the DTC vector table for the lower 16 bits. The placement in order from the register information start address in normal mode is DTMR, DTCRA, 4 bytes empty (no effect on DTC operation), DTSAR, then DTDAR. In repeat mode it is DTMR, DTCRA, DTIAR, DTSAR, and DTDAR. In block transfer mode, it is DTMR, DTCRA, 2 bytes empty (no effect on DTC operation), DTCRB, DTSAR, then DTDAR. Fundamentally, certain RAM areas are designated for addresses storing register information. |
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