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SH7041A bảng dữ liệu(PDF) 792 Page - Renesas Technology Corp

tên linh kiện SH7041A
Giải thích chi tiết về linh kiện  Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
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754
25.3.2
Control Signal Timing
Table 25.5
Control Signal Timing (Conditions: V
CC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%,
AV
CC = VCC ± 10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, Ta = –20 to +75° C)
Item
Symbol
Min
Max
Unit
Figure
RES rise/fall
t
RESr, t RESf
—
200
ns
25.4
RES pulse width
t
RESW
20
—
t
cyc
MRES pulse width
t
MRESW
20
—
t
cyc
NMI rise/fall
t
NMIr, t NMIf
—
200
ns
25.5
RES setup time*
t
RESS
35
—
ns
25.4,
MRES setup time*
t
MRESS
35
—
ns
25.5
NMI setup time*
t
NMIS
35
—
ns
IRQ7–IRQ0 setup time (edge detection)
t
IRQES
35
—
ns
IRQ7–IRQ0 setup time (level detection)
t
IRQLS
35
—
ns
NMI hold time
t
NMIH
35
—
ns
25.5
IRQ7–IRQ0 hold time
t
IRQEH
35
—
ns
IRQOUT output delay time
t
IRQOD
—
35
ns
25.6
Bus request setup time
t
BRQS
35
—
ns
25.7
Bus acknowledge delay time 1
t
BACKD1
—35
ns
Bus acknowledge delay time 2
t
BACKD2
—35
ns
Bus three-state delay time
t
BZD
—35
ns
Note: * The
RES, MRES, NMI, BREQ, and IRQ7–IRQ0 signals are asynchronous inputs, but
when thesetup times shown here are provided, the signals are considered to have
produced changes at clock rise (for
RES, MRES, BREQ) or clock fall (for NMI and IRQ7–
IRQ0). If the setup times are not provided, recognition is delayed until the next clock rise
or fall.



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