SH7041A datasheet(785/923 Pages) RENESAS

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Table 24.3

Module

Registers Initialized

Registers that

Retain Data

Registers with

Undefined Contents

Pin function controller

(PFC)

—

All registers

—

I/O port (I/O)

—

All registers

—

Power-down state

—

Standby control

—

24.4.2

Canceling the Standby Mode

The standby mode is canceled by an NMI interrupt, a power-on reset, or a manual reset.

Cancellation by an NMI: Clock oscillation starts when a rising edge or falling edge (selected by

the NMI edge select bit (NMIE) of the interrupt control register (ICR) of the INTC) is detected in

the NMI signal. This clock is supplied only to the watchdog timer (WDT). A WDT overflow

occurs if the time established by the clock select bits (CKS2–CKS0) in the TCSR of the WDT

elapses before transition to the standby mode. The occurrence of this overflow is used to indicate

that the clock has stabilized, so the clock is supplied to the entire chip, the standby mode is

canceled, and NMI exception processing begins.

When canceling standby mode with NMI interrupts, set the CKS2–CKS0 bits so that the WDT

overflow period is longer than the oscillation stabilization time.

When canceling standby mode with an NMI pin set for falling edge, be sure that the NMI pin level

upon entering standby (when the clock is halted) is high level, and that the NMI pin level upon

returning from standby (when the clock starts after oscillation stabilization) is low level. When

canceling standby mode with an NMI pin set for rising edge, be sure that the NMI pin level upon

entering standby (when the clock is halted) is low level, and that the NMI pin level upon returning

from standby (when the clock starts after oscillation stabilization) is high level.

Cancellation by a Power-On Reset: A power-on reset caused by setting the

RES pin to low level

cancels the standby mode.

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