SH7041A datasheet(451/923 Pages) RENESAS

tên linh kiện	SH7041A

Giải thích chi tiết về linh kiện	Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

PDF	923 Pages

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• In PWM mode 2, since a waveform is not output to the cycle register pin, setting TIOR will

not initialize the pins. If initialization is required, carry it out in normal mode, then switch to

PWM mode 2.

• In normal mode or PWM mode 2, if TGRC and TGRD operate as buffer registers, setting

TIOR will not initialize the buffer register pins. If initialization is required, clear buffer mode,

carry out initialization, then set buffer mode again.

• In PWM mode 1, if either TGRC or TGRD operates as a buffer register, setting TIOR will not

initialize the TGRC pin. To initialize the TGRC pin, clear buffer mode, carry out initialization,

then set buffer mode again.

• When making a transition to a mode (CPWM, RPWM) in which the pin output level is selected

by the timer output control register (TOCR) setting, switch to normal mode and perform

initialization with TIOR, then restore TIOR to its initial value, and temporarily disable channel

3 and 4 output with the timer output master enable register (TOER). Then operate the unit in

accordance with the mode setting procedure (TOCR setting, TMDR setting, TOER setting).

Pin initialization procedures are described below for the numbered combinations in table 12.19.

The active level is assumed to be low.

Note:

Channel number is substituted for * indicated in this article.

SH7041A bảng dữ liệu(PDF) 451 Page - Renesas Technology Corp