SH7041A datasheet(399/923 Pages) RENESAS

tên linh kiện	SH7041A

Giải thích chi tiết về linh kiện	Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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• PWM cycle setting

In complementary PWM mode, the PWM pulse cycle is set in two registers—TGR3A, in

which the TCNT3 upper limit value is set, and TCDR, in which the TCNT4 upper limit value

is set. The settings should be made so as to achieve the following relationship between these

two registers:

TGR3A set value = TCDR set value + TDDR set value

The TGR3A and TCDR settings are made by setting the values in buffer registers TGR3C and

TCBR. The values set in TGR3C and TCBR are transferred simultaneously to TGR3A and

TCDR in accordance with the transfer timing selected with bits MD3–MD0 in the timer mode

The updated PWM cycle is reflected from the next cycle when the data update is performed at

the crest, and from the current cycle when performed in the trough. Figure 12.41 illustrates the

operation when the PWM cycle is updated at the crest.

See the following section, Register data updating, for the method of updating the data in each

buffer register.

Counter value

TGR3C

update

TGR3A

update

TGR3A

TCNT3

TCNT4

Time

Figure 12.41 Example of PWM Cycle Updating

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