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SH7041A bảng dữ liệu(PDF) 345 Page - Renesas Technology Corp

tên linh kiện SH7041A
Giải thích chi tiết về linh kiện  Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
PDF  923 Pages
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7041A bảng dữ liệu(HTML) 345 Page - Renesas Technology Corp

Back Button SH7041A Datasheet HTML 341Page - Renesas Technology Corp SH7041A Datasheet HTML 342Page - Renesas Technology Corp SH7041A Datasheet HTML 343Page - Renesas Technology Corp SH7041A Datasheet HTML 344Page - Renesas Technology Corp SH7041A Datasheet HTML 345Page - Renesas Technology Corp SH7041A Datasheet HTML 346Page - Renesas Technology Corp SH7041A Datasheet HTML 347Page - Renesas Technology Corp SH7041A Datasheet HTML 348Page - Renesas Technology Corp SH7041A Datasheet HTML 349Page - Renesas Technology Corp Next Button
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Channels 1, 2: TIER1, TIER2:
Bit:
7
6
5
4
3
2
1
0
TTGE
—
TCIEU
TCIEV
—
—
TGIEB
TGIEA
Initial value:
0
1
0
0
0
0
0
0
R/W:
R/W
R
R/W
R/W
R
R
R/W
R/W
Channels 3, 4: TIER3, TIER4:
Bit:
7
6
5
4
3
2
1
0
TTGE
—
—
TCIEV
TGIED
TGIEC
TGIEB
TGIEA
Initial value:
0
1
0
0
0
0
0
0
R/W:
R/W
R
R
R/W
R/W
R/W
R/W
R/W
• Bit 7—A/D Conversion Start Request Enable (TTGE): Enables or disables generation of an
A/D conversion start request by a TGRA register input capture/compare-match.
Bit 7: TTGE
Description
0
Disable A/D conversion start requests (initial value)
1
Enable A/D conversion start request generation
• Bit 6—Reserved: This bit is reserved. It always reads as 0, and cannot be modified.
• Bit 5—Underflow Interrupt Enable (TCIEU): Enables or disables interrupt requests when the
underflow flag (TCFU) of the channel 1, 2 timer status register (TSR) is set to 1.
This bit is reserved for channels 0, 3, and 4. It always reads as 0. The write value should
always be 1.
Bit 5: TCIEU
Description
0
Disable UDF interrupt requests (TCIU) (initial value)
1
Enable UDF interrupt requests (TCIU)
• Bit 4—Overflow Interrupt Enable (TCIEV): Enables or disables interrupt requests when the
overflow flag TCFV of the timer status register (TSR) is set to 1.
Bit 4: TCIEVDescription
0
Disable TCFV interrupt requests (TCIV) (initial value)
1
Enable TCFV interrupt requests (TCIV)



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