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LTC4162EUFD-FSTM#PBF bảng dữ liệu(PDF) 50 Page - Analog Devices

tên linh kiện LTC4162EUFD-FSTM#PBF
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LTC4162EUFD-FSTM#PBF bảng dữ liệu(HTML) 50 Page - Analog Devices

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50
LTC4162-F
Rev A
For more information www.analog.com
PACKAGE DESCRIPTION
4.00
±0.10
(2 SIDES)
2.50 REF
5.00
±0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGHD-3).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40
±0.10
27
28
1
2
BOTTOM VIEW—EXPOSED PAD
3.50 REF
0.75
±0.05
R = 0.115
TYP
R = 0.05
TYP
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER
0.25
±0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UFD28) QFN 0816 REV C
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70
±0.05
0.25
±0.05
0.50 BSC
2.50 REF
3.50 REF
4.10
±0.05
5.50
±0.05
2.65
±0.05
3.10
±0.05
4.50
±0.05
PACKAGE OUTLINE
2.65
±0.10
3.65
±0.10
3.65
±0.05
UFD Package
28-Lead Plastic QFN (4mm
× 5mm)
(Reference LTC DWG # 05-08-1712 Rev C)



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