DS31256+ datasheet(111/183 Pages) MAXIM

111 / 183 page

DS31256 256-Channel, High-Throughput HDLC Controller

111 of 183

Figure 9-13. Transmit DMA Priority Packet Handling

Buffer 1

Packet 1

1st Descriptor

(EOF=0/CV=0)

Buffer 2

Packet 1

2nd Descriptor

(EOF=0/CV=0)

Buffer 3

Packet 1

Last Descriptor

(EOF=1/CV=1)

Buffer 1

Packet 2

Last Descriptor

(EOF=1/CV=0)

Buffer 1

Pri. Packet 1

1st Descriptor

(EOF=0/CV=0)

Buffer 2

Pri. Packet 1

Last Descriptor

(EOF=1/CV=1)

Buffer 1

Pri. Packet 2

Last Descriptor

(EOF=1/CV=0)

Buffer 1

Pri. Packet 3

Last Descriptor

(EOF=1/CV=0)

Buffer 1

Pri. Packet 4

1st Descriptor

(EOF=0/CV=0)

Buffer 2

Pri. Packet 4

2nd Descriptor

(EOF=0/CV=0)

Buffer 3

Pri. Packet 4

Last Descriptor

(EOF=1/CV=0)

Next Descriptor Pointer

Start Descriptor Pointer

Transmit DMA Configuration RAM

Normal

Path if No

Priority

Packets

Had

Occurred

Service

Priority

Packets

All Priority Packets Have Been Serviced

Next Pending Descriptor Pointer

Last Pending Descriptor Pointer

Next Pending Descriptor Pointer

Next Descriptor Pointer

Last Pending Descriptor Pointer

Standard Queue Pointers

Priority Queue Pointers

Note 1: The start descriptor pointer field in the transmit DMA configuration RAM is used by both the normal and

priority pending queues.

See

Note 1

PV = 1

Next Pending

Descriptor Pointer

stored within the

Packet Descriptor

Standard

Packet Chain

Column 1

Priority

Packet Chain

Column 2

Priority

Packet Chain

Column 3

Priority

Packet Chain

Column 4

DS31256+ bảng dữ liệu(PDF) 111 Page - Maxim Integrated Products

DS31256+ bảng dữ liệu(HTML) 111 Page - Maxim Integrated Products

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL