IMX8DXAEC datasheet(68/143 Pages) NXP

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Electrical characteristics

i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020

NXP Semiconductors

4.10.4

Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC) AC

Timing

This section describes the electrical information of the uSDHC, including:

•

SD3.1/eMMC5.1 High-Speed mode AC Timing

•

eMMC5.1 DDR 52 mode/SD3.1 DDR 50 mode timing

•

HS400 AC timing—eMMC 5.1 only

•

HS200 Mode Timing

•

SDR50/SDR104 AC Timing

FSR output delay

x ck

i ck a

RX data pins - setup requirement

—x ck

i ck

t10

RX data pins - hold requirement

—x ck

i ck

t11

FSR - setup requirement

—x ck

i ck a

t12

FSR - hold requirement

—x ck

i ck a

t13

Flags - setup requirement

—x ck

i ck s

t14

Flags - hold requirement

—x ck

i ck s

—

RX_HF_CLK / TX_HX_CLK clock cycle

—

TX_HF_CLK input to SCKT

—

RX_HF_CLK input to SCKR

—

1 i ck = internal clock

x ck = external clock

i ck a = internal clock, asynchronous mode (SCKT and SCKR are two different clocks)

i ck s = internal clock, synchronous mode (SCKT and SCKR are the same clock)

Table 63. Enhanced Serial Audio Interface (ESAI) Timing (continued)

Parameters

Min

Max

Condition1

Unit

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