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DS2152 bảng dữ liệu(PDF) 34 Page - Maxim Integrated Products

tên linh kiện DS2152
Giải thích chi tiết về linh kiện  Enhanced T1 Single-Chip Transceiver
PDF  97 Pages
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DS2152 bảng dữ liệu(HTML) 34 Page - Maxim Integrated Products

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DS2152
34 of 97
RIR3: RECEIVE INFORMATION REGISTER 3 (Address = 10 Hex)
(MSB)
(LSB)
RL1
RL0
JALT
LORC
FRCL
—
—
—
SYMBOL
POSITION
NAME AND DESCRIPTION
RL1
RIR3.7
Receive Level Bit 1. See Table 5-1.
RL0
RIR3.6
Receive Level Bit 0. See Table 5-1.
JALT
RIR3.5
Jitter Attenuator Limit Trip. Set when the jitter attenuator
FIFO reaches to within 4 bits of its limit; useful for debugging
jitter attenuation operation.
LORC
RIR3.4
Loss of Receive Clock. Set when the RCLKI pin has not
transitioned for at least 2
µs (3µs ±1µs).
FRCL
RIR3.3
Framer Receive Carrier Loss. Set when 192 consecutive 0s
have been received at the RPOSI and RNEGI pins; allowed to be
cleared when 14 or more 1s out of 112 possible bit positions are
received.
—
RIR3.2, RIR3.1,
RIR3.0
Not Assigned. Could be any value when read.
Table 5-1. Receive T1 Level Indication
RL1
RL0
TYPICAL LEVEL
RECEIVED
(dB)
0
0
+2 to -7.5
0
1
-7.5 to -15
1
0
-15 to -22.5
1
1
less than -22.5



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