MCIMX6DP4AVT2AB datasheet(119/160 Pages) NXP

tên linh kiện	MCIMX6DP4AVT2AB

Giải thích chi tiết về linh kiện	i.MX 6DualPlus/6QuadPlus Applications Processors Industrial Products

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Electrical Characteristics

i.MX 6DualPlus/6QuadPlus Applications Processors Industrial Products, Rev. 3, 11/2018

NXP Semiconductors

119

Figure 84. SPDIF_SR_CLK Timing Diagram

Figure 85. SPDIF_ST_CLK Timing Diagram

4.12.19 SSI Timing Parameters

This section describes the timing parameters of the SSI module. The connectivity of the serial

synchronous interfaces are summarized in Table 72.

NOTE

The terms WL and BL used in the timing diagrams and tables refer to Word

Length (WL) and Bit Length (BL).

Table 72. AUDMUX Port Allocation

Port

Signal Nomenclature

Type and Access

AUDMUX port 1

SSI 1

Internal

AUDMUX port 2

SSI 2

Internal

AUDMUX port 3

AUD3

External – AUD3 I/O

AUDMUX port 4

AUD4

External – EIM or CSPI1 I/O through IOMUXC

AUDMUX port 5

AUD5

External – EIM or SD1 I/O through IOMUXC

AUDMUX port 6

AUD6

External – EIM or DISP2 through IOMUXC

AUDMUX port 7

SSI 3

Internal

SPDIF_SR_CLK

(Output)

srckp

srckph

srckpl

SPDIF_ST_CLK

(Input)

stclkp

stclkph

stclkpl

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